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ADC08004-1LCD Datasheet PDF - NXP

Part Number ADC08004-1LCD
Description CMOS 8-bit A/D converters
Manufacturers NXP 
Logo NXP Logo 



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ADC08004-1LCD datasheet, circuit
INTEGRATED CIRCUITS
ADC0803/0804
CMOS 8-bit A/D converters
Product data
Supersedes data of 2001 Aug 03
2002 Oct 17
Philips
Semiconductors

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ADC08004-1LCD equivalent
Philips Semiconductors
CMOS 8-bit A/D converters
Product data
ADC0803/0804
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TO FROM
TEST CONDITIONS
Conversion time
fCLK Clock frequency1
Clock duty cycle1
fCLK = 1 MHz1
CR Free-running conversion rate
CS = 0, fCLK = 1 MHz
INTR tied to WR
tW(WR)L
tACC
t1H, t0H
Start pulse width
Access time
3-State control
Output
Output
RD
RD
CS = 0
CS = 0, CL = 100 pF
CL = 10 pF, RL = 10 k
See 3-State test circuit
tW1, tR1
INTR delay
INTR
WD
or RD
CIN Logic input=capacitance
COUT
3-State output capacitance
NOTE:
1. Accuracy is guaranteed at fCLK = 1 MHz. Accuracy may degrade at higher clock frequencies.
LIMITS
Min Typ Max
66 73
0.1 1.0 3.0
40 60
UNIT
µs
MHz
%
13690 conv/s
30
75 100
ns
ns
70 100
ns
100 150
5 7.5
5 7.5
ns
pF
pF
FUNCTIONAL DESCRIPTION
These devices operate on the Successive Approximation principle.
Analog switches are closed sequentially by successive
approximation logic until the input to the auto-zero comparator
[ VIN(+)–VIN(–) ] matches the voltage from the decoder. After all bits
are tested and determined, the 8-bit binary code corresponding to
the input voltage is transferred to an output latch. Conversion begins
with the arrival of a pulse at the WR input if the CS input is low. On
the High-to-Low transition of the signal at the WR or the CS input,
the SAR is initialized, the shift register is reset, and the INTR output
is set high. The A/D will remain in the reset state as long as the CS
and WR inputs remain low. Conversion will start from one to eight
clock periods after one or both of these inputs makes a Low-to-High
transition. After the conversion is complete, the INTR pin will make a
High-to-Low transition. This can be used to interrupt a processor, or
otherwise signal the availability of a new conversion result. A read
(RD) operation (with CS low) will clear the INTR line and enable the
output latches. The device may be run in the free-running mode as
described later. A conversion in progress can be interrupted by
issuing another start command.
Digital Control Inputs
The digital control inputs (CS, WR, RD) are compatible with
standard TTL logic voltage levels. The required signals at these
inputs correspond to Chip Select, START Conversion, and Output
Enable control signals, respectively. They are active-Low for easy
interface to microprocessor and microcontroller control buses. For
applications not using microprocessors, the CS input (Pin 1) can be
grounded and the A/D START function is achieved by a
negative-going pulse to the WR input (Pin 3). The Output Enable
function is achieved by a logic low signal at the RD input (Pin 2),
which may be grounded to constantly have the latest conversion
present at the output.
ANALOG OPERATION
Analog Input Current
The analog comparisons are performed by a capacitive charge
summing circuit. The input capacitor is switched between VIN(+)4
and VIN(–), while reference capacitors are switched between taps on
the reference voltage divider string. The net charge corresponds to
the weighted difference between the input and the most recent total
value set by the successive approximation register.
The internal switching action causes displacement currents to flow
at the analog inputs. The voltage on the on-chip capacitance is
switched through the analog differential input voltage, resulting in
proportional currents entering the VIN(+) input and leaving the VIN(–)
input. These transient currents occur at the leading edge of the
internal clock pulses. They decay rapidly so do not inherently cause
errors as the on-chip comparator is strobed at the end of the clock
period.
Input Bypass Capacitors and Source Resistance
Bypass capacitors at the input will average the charges mentioned
above, causing a DC and an AC current to flow through the output
resistance of the analog signal sources. This charge pumping action
is worse for continuous conversions with the VIN(+) input at full
scale. This current can be a few microamps, so bypass capacitors
should NOT be used at the analog inputs of the VREF/2 input for
high resistance sources (> 1 k). If input bypass capacitors are
desired for noise filtering and a high source resistance is desired to
minimize capacitor size, detrimental effects of the voltage drop
across the input resistance can be eliminated by adjusting the full
scale with both the input resistance and the input bypass capacitor
in place. This is possible because the magnitude of the input current
is a precise linear function of the differential voltage.
2002 Oct 17
5

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