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AD9775 Datasheet PDF - Analog Devices

Part Number AD9775
Description Digital-to-Analog Converter
Manufacturers Analog Devices 
Logo Analog Devices Logo 

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AD9775 datasheet, circuit
14-Bit, 160 MSPS, 2×/4×/8× Interpolating
Dual TxDAC+® Digital-to-Analog Converter
AD9775
FEATURES
14-bit resolution, 160 MSPS/400 MSPS input/output
data rate
Selectable 2×/4×/8× interpolating filter
Programmable channel gain and offset adjustment
fS/4, fS/8 digital quadrature modulation capability
Direct IF transmission mode for 70 MHz + IFs
Enables image rejection architecture
Fully compatible SPI® port
Excellent ac performance
SFDR: −71 dBc @ 2 MHz to 35 MHz
W-CDMA ACPR: −71 dB @ IF = 19.2 MHz
Internal PLL clock multiplier
Selectable internal clock divider
Versatile clock input
Differential/single-ended sine wave or TTL/CMOS/LVPECL
compatible
Versatile input data interface
Twos complement/straight binary data coding
Dual-port or single-port interleaved input data
Single 3.3 V supply operation
Power dissipation: 1.2 W @ 3.3 V typical
On-chip, 1.2 V reference
80-lead, thin quad flat package, exposed pad (TQFP_EP)
APPLICATIONS
Communications
Analog quadrature modulation architecture
3G, multicarrier GSM, TDMA, CDMA systems
Broadband wireless, point-to-point microwave radios
Instrumentation/ATE
FUNCTIONAL BLOCK DIAGRAM
AD9775
14
I AND Q
NONINTERLEAVED
OR INTERLEAVED
DATA
14
DATA
ASSEMBLER
HALF-
BAND
FILTER1*
I 16
LATCH
16
HALF- HALF-
BAND BAND
FILTER2* FILTER3*
16 16
Q 16
LATCH
16
16 16
COS
SIN
fDAC/2, 4, 8
SIN
IMAGE
REJECTION/
DUAL DAC
MODE
BYPASS
MUX
WRITE
SELECT
MUX
CONTROL
CLOCK OUT
/2
SPI INTERFACE AND
CONTROL REGISTERS
/2
/2
* HALF-BAND FILTERS ALSO CAN BE
CONFIGURED FOR ZERO STUFFING ONLY
FILTER
BYPASS
MUX
/2
COS
(fDAC)
PRESCALER
PHASE DETECTOR
AND VCO
PLL CLOCK MULTIPLIER AND CLOCK DIVIDER
Figure 1.
IDAC
GAIN
DAC
OFFSET
DAC
I/Q DAC
GAIN/OFFSET
REGISTERS
IDAC
IOUT
DIFFERENTIAL
CLK
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.

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AD9775 equivalent
AD9775
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
DC Accuracy1
Integral Nonlinearity
Differential Nonlinearity
ANALOG OUTPUT (for 1R and 2R Gain Setting Modes)
Offset Error
Gain Error (with Internal Reference)
Gain Matching
Full-Scale Output Current2
Output Compliance Range
Output Resistance
Output Capacitance
Gain, Offset Cal DACs, Monotonicity Guaranteed
REFERENCE OUTPUT
Reference Voltage
Reference Output Current3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
Small Signal Bandwidth
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (with Internal Reference)
Reference Voltage Drift
POWER SUPPLY
AVDD
Voltage Range
Analog Supply Current (IAVDD)4
IAVDD in SLEEP Mode
CLKVDD
Voltage Range
Clock Supply Current (ICLKVDD)4
CLKVDD (PLL ON)
Clock Supply Current (ICLKVDD)
DVDD
Voltage Range
Digital Supply Current (IDVDD)4
Nominal Power Dissipation
PDIS 5
PDIS IN PWDN
Power Supply Rejection Ratio—AVDD
OPERATING RANGE
Min
14
−5
−3
−0.02
−1.0
−1.0
2
−1.0
Typ
±1.5
±1.0
±0.01
±0.1
200
3
Max
+5
+3
+0.02
+1.0
+1.0
20
+1.25
Unit
Bits
LSB
LSB
% of FSR
% of FSR
% of FSR
mA
V
pF
1.14 1.20 1.26 V
100 nA
0.1 1.25 V
7 kΩ
0.5 MHz
0 ppm of FSR/°C
50 ppm of FSR/°C
±50 ppm/°C
3.1 3.3 3.5 V
72.5 76
mA
23.3 26
mA
3.1 3.3 3.5 V
8.5 10.0 mA
23.5 mA
3.1 3.3 3.5 V
34 41 mA
380 410 mW
1.75 W
6.0 mW
±0.4 % of FSR/V
−40 +85 °C
1 Measured at IOUTA driving a virtual ground.
2 Nominal full-scale current, IOUTFS, is 32 × the IREF current.
3 Use an external amplifier to drive any external load.
4 100 MSPS fDAC with fOUT = 1 MHz, all supplies = 3.3 V, no interpolation, no modulation.
5 400 MSPS fDAC = 50 MSPS, fS/2 modulation, PLL enabled.
Rev. E | Page 5 of 56

5 Page
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Information Total 30 Pages
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