A28F010 PDF Datasheet - 1024K (128K x 8) CMOS FLASH MEMORY - Intel Corporation

Part Number A28F010
Description 1024K (128K x 8) CMOS FLASH MEMORY
Manufacturers Intel Corporation 
Logo Intel Corporation Logo 
Preview ( 23 pages )
A28F010 datasheet, circuit
1024K (128K x 8) CMOS FLASH MEMORY
Y Automotive Temperature Range
b40 C to a125 C
Y Flash Memory Electrical Chip-Erase
1 Second Typical Chip-Erase
Y Quick-Pulse Programming Algorithm
10 ms Typical Byte-Program
2 Second Chip-Program
Y 1 000 Erase Program Cycles Minimum
over Automotive Temperature Range
Y 12 0V g5% VPP
Y High-Performance Read
120 ns Maximum Access Time
Y CMOS Low Power Consumption
30 mA Maximum Active Current
300 mA Maximum Standby Current
Y Integrated Program Erase Stop Timer
Y Command Register Architecture for
Microprocessor Microcontroller
Compatible Write Interface
Y Noise Immunity Features
g10% VCC Tolerance
Maximum Latch-Up Immunity
through EPI Processing
Y ETOXTM III Flash Nonvolatile Memory
EPROM-Compatible Process Base
High-Volume Manufacturing
Y JEDEC-Standard Pinouts
32-Pin Plastic DIP
32-Lead PLCC
(See Packaging Spec Order 231369)
Intel’s 28F010 CMOS flash memory offers the most cost-effective and reliable alternative for read write
random access nonvolatile memory The 28F010 adds electrical chip-erasure and reprogramming to familiar
EPROM technology Memory contents can be rewritten in a test socket in a PROM-programmer socket on-
board during subassembly test in-system during final test and in-system after-sale The 28F010 increases
memory flexibility while contributing to time- and cost-savings
The 28F010 is a 1024-kilobit nonvolatile memory organized as 131 072 bytes of 8 bits Intel’s 28F010 is
offered in 32-pin Plastic DIP or 32-lead PLCC packages Pin assignments conform to JEDEC standards
Extended erase and program cycling capability is designed into Intel’s ETOXTM III (EPROM Tunnel Oxide)
process technology Advanced oxide processing an optimized tunneling structure and lower electric field
combine to extend reliable cycling beyond that of traditional EEPROMs With the 12 0V VPP supply the
28F010 performs a minimum of 1 000 erase and program cycles well within the time limits of the Quick-Pulse
Programming and Quick-Erase algorithms
Intel’s 28F010 employs advanced CMOS circuitry for systems requiring high-performance access speeds low
power consumption and immunity to noise Its 120 nanosecond access time provides no-WAIT-state perform-
ance for a wide range of microprocessors and microcontrollers Maximum standby current of 300 mA trans-
lates into power savings when the device is deselected Finally the highest degree of latch-up protection is
achieved through Intel’s unique EPI processing Prevention of latch-up is provided for stresses up to 100 mA
on address and data pins from b1V to VCC a 1V
With Intel’s ETOX III process base the 28F010 leverages years of EPROM experience to yield the highest
levels of quality reliability and cost-effectiveness
In order to meet the rigorous environmental requirements of automotive applications Intel offers the 28F010 in
extended automotive temperature range Read and write characteristics are guaranteed over the range of
b40 C to a125 C ambient
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
November 1995
Order Number 290266-004

1 page

A28F010 pdf, schematic
Figure 1 28F010 Block Diagram
The Intel Automotive Flash memories have received
additional processing to enhance product character-
istics The automotive temperature range is b40 C
to a125 C during the read write erase program
290266 – 1
Packaging Options
Plastic DIP

2 Page

A28F010 equivalent
Figure 3 28F010 in a 80C186 System
290266 – 4
Flash-memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming The
28F010 introduces a command register to manage
this new functionality The command register allows
for 100% TTL-level control inputs fixed power sup-
plies during erasure and programming and maxi-
mum EPROM compatibility
In the absence of high voltage on the VPP pin the
28F010 is a read-only memory Manipulation of the
external memory-control pins yields the standard
EPROM read standby output disable and Intelli-
gent Identifier operations
The same EPROM read standby and output disable
operations are available when high voltage is ap-
plied to the VPP pin In addition high voltage on VPP
enables erasure and programming of the device All
functions associated with altering memory con-
tents Intelligent Identifier erase erase verify pro-
gram and program verify are accessed via the
command register
Commands are written to the register using standard
microprocessor write timings Register contents
serve as input to an internal state-machine which
controls the erase and programming circuitry Write
cycles also internally latch addresses and data
needed for programming or erase operations With
the appropriate command written to the register
standard microprocessor read timings output array
data access the Intelligent Identifier codes or out-
put data for erase and program verification
Integrated Program Erase Stop Timer
Successive command write cycles define the dura-
tions of program and erase operations specifically
the program or erase time durations are normally
terminated by associated program or erase verify
commands An integrated stop timer provides simpli-
fied timing control over these operations thus elimi-
nating the need for maximum program erase timing
specifications Program and erase pulse durations
are minimums only When the stop timer terminates
a program or erase operation the device enters an
inactive state and remains inactive until receiving the
appropriate verify or reset command
Write Protection
The command register is only alterable when VPP is
at high voltage Depending upon the application the
system designer may choose to make the VPP pow-
er supply switchable available only when memory
updates are desired When high voltage is removed

5 Page

A28F010 diode, scr
ming Characteristics and Waveforms for specific
timing parameters
Program-Verify Command
The 28F010 is programmed on a byte-by-byte basis
Byte programming may occur sequentially or at ran-
dom Following each programming operation the
byte just programmed must be verified
The program-verify operation is initiated by writing
C0H into the command register The register write
terminates the programming operation with the ris-
ing edge of its Write-Enable pulse The program-ver-
ify operation stages the device for verification of the
byte last programmed No new address information
is latched
The 28F010 applies an internally-generated margin
voltage to the byte A microprocessor read cycle
outputs the data A successful comparison between
the programmed byte and true data means that the
byte is successfully programmed Programming then
proceeds to the next desired byte location Figure 4
the 28F010 Quick-Pulse Programming algorithm il-
lustrates how commands are combined with bus op-
erations to perform byte programming Refer to A C
Programming Characteristics and Waveforms for
specific timing parameters
Reset Command
A reset command is provided as a means to safely
abort the erase- or program-command sequences
Following either set-up command (erase or program)
with two consecutive writes of FFH will safely abort
the operation Memory contents will not be altered
A valid command must then be written to place the
device in the desired state
EEPROM cycling failures have always concerned
users The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions To combat this some sup-
pliers have implemented redundancy schemes re-
ducing cycling failures to insignificant levels Howev-
er redundancy requires that cell size be doubled
an expensive solution
Intel has designed extended cycling capability into
its ETOX-II flash memory technology Resulting im-
provements in cycling reliability come without in-
creasing memory cell size or complexity First an
advanced tunnel oxide increases the charge carry-
ing ability ten-fold Second the oxide area per cell
subjected to the tunneling electric field is one-tenth
that of common EEPROMs minimizing the probabili-
ty of oxide defects in the region Finally the peak
electric field during erasure is approximately 2 MV
cm lower than EEPROM The lower electric field
greatly reduces oxide stress and the probability of
failure increasing time to wearout by a factor of
100 000 000
The device is programmed and erased using Intel’s
Quick-Pulse Programming and Quick-Erase algo-
rithms Intel’s algorithmic approach uses a series of
operations (pulses) along with byte verification to
completely and reliably erase and program the de-
The Quick-Pulse Programming algorithm uses pro-
gramming operations of 10 ms duration Each opera-
tion is followed by a byte verification to determine
when the addressed byte has been successfully pro-
grammed The algorithm allows for up to 25 pro-
gramming operations per byte although most bytes
verify on the first or second operation The entire
sequence of programming and byte verification is
performed with VPP at high voltage Figure 4 illus-
trates the Quick-Pulse Programming algorithm
Intel’s Quick-Erase algorithm yields fast and reliable
electrical erasure of memory contents The algo-
rithm employs a closed-loop flow similar to the
Quick-Pulse Programming algorithm to simulta-
neously remove charge from all bits in the array
Erasure begins with a read of memory contents The
28F010 is erased when shipped from the factory
Reading FFH data from the device would immedi-
ately be followed by device programming
For devices being erased and reprogrammed uni-
form and reliable erasure is ensured by first pro-
gramming all bits in the device to their charged state
(Data e 00H) This is accomplished using the
Quick-Pulse Programming algorithm in approxi-
mately two seconds
Erase execution then continues with an initial erase
operation Erase verification (data e FFH) begins at
address 0000H and continues through the array to
the last address or until data other than FFH is en-
countered With each erase operation an increasing
number of bytes verify to the erased state Erase
efficiency may be improved by storing the address of
the last byte verified in a register Following the next
erase operation verification starts at that stored ad-
dress location Erasure typically occurs in one sec-
ond Figure 5 illustrates the Quick-Erase algorithm

9 Page

A28F010 transistor, igbt
Figure 11 AC Waveforms for Programming Operations

21 Page

Information Total 23 Pages
Download[ A28F010.PDF Datasheet ]

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A28F010The function of this parts is a 1024K (128K x 8) CMOS FLASH MEMORY.Intel Corporation
Intel Corporation

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