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A26E001AV PDF Datasheet - AMIC Technology

Part Number A26E001AV
Description 2M and 256K MaskRAM
Manufacturers AMIC Technology 
Logo AMIC Technology Logo 
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A26E001AV datasheet, circuit
Document Title
2M and 256K MaskRAM
Revision History
Rev. No.
2.0
2.1
History
Final spec release
Change tOE speed from 150ns to 200ns
A26E001A
2M and 256K MaskRAM
Issue Date
October 12, 1998
November 20, 1998
Remark
Final
(November, 1998, Version 2.1)
AMIC Technology, Inc.

1 page
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A26E001AV pdf, schematic
A26E001A
2M and 256K MaskRAM
Features
n Power supply range: 1.8V to 3.3V
n Access time: 450 ns (max.)
n Current:
Low power version: Operating: 4mA (max.)
Standby: 10µA (max.)
n Extended operating temperature range: -25°C to 85°C
General Description
The A26E001A is a low operating current 262,144 x 8 bit
CMOS MASK ROM and 32,768 x 8 bit CMOS SRAM
integrated into one chip. It operates on a low power
supply voltage from 1.8V to 3.3V, with two chip selects
to enable the MASK ROM or SRAM independently.
Inputs and three-state outputs are CMOS compatible and
allow for direct interfacing with common system bus
structures.
Pin Configuration
n Full static operation, no clock or refreshing required
n All inputs and outputs are CMOS compatible
n Common I/O using three-state output
n Data retention voltage: 1.6V (min.)
n Available in 32-pin TSOP and sTSOP packages
Minimum standby power is drawn by this device when
ROMCE and RAMCE are at a high level, independent
of the other input levels.
Data retention is guaranteed at a power supply voltage
as low as 1.6V.
Pin Description
A11
A9
A8
A13
A14
A17
RAMCE
VCC
WE
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A11
A9
A8
A13
A14
A17
RAMCE
VCC
WE
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A26E001AV
32 OE
31 A10
30 ROMCE
29 D7
28 D6
27 D5
26 D4
25 D3
24 GND
23 D2
22 D1
21 D0
20 A0
19 A1
18 A2
17 A3
A26E001AX
32 OE
31 A10
30 ROMCE
29 D7
28 D6
27 D5
26 D4
25 D3
24 GND
23 D2
22 D1
21 D0
20 A0
19 A1
18 A2
17 A3
Pin No.
Symbol
Description
1 - 6, 10 - 20, 31 A0 - A17 Address Inputs
7 RAMCE SRAM Enable
9 WE Write Enable
21 - 23, 25 - 29 D0 - D7 Data Input/Outputs
30 ROMCE ROM Enable
32 OE Output Enable
8
VCC
Power Supply
24 GND Ground
(November, 1998, Version 21)
1 AMIC Technology, Inc.

2 Page
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A26E001AV equivalent
Capacitance
Symbol
Parameter
Min.
CI* Input Capacitance
CO* Input/Output Capacitance
* These parameters are sampled and not 100% tested.
AC Characteristics (ROM/SRAM Selection)
Symbol
Parameter
tRTS ROMCE Disable to RAMCE Enable Time
tSTR RAMCE Disable to ROMCE Enable Time
A26E001A
Max.
6
8
Unit
pF
pF
(TA = 25°C, f = 1.0MHz)
Conditions
TA = 25°C
f = 1.0MHz
(TA = -25°C to +85°C, VCC = 1.8V to 3.3V)
Min.
Max.
Unit
10 - ns
10 - ns
AC Characteristics (ROM Selected)
(TA = -25°C to +85°C, VCC = 1.8V to 3.3V)
Symbol
Parameter
Min.
Max.
Unit
tRC Read Cycle Time
500 - ns
tAA Address Access Time
- 450 ns
tACE ROMCE Chip Enable Access Time
- 450 ns
tOE Output Enable to Output Valid
- 200 ns
tCLZ ROMCE Chip Enable to Output in Low Z
10 - ns
tOLZ Output Enable to Output in Low Z
10 - ns
tCHZ ROMCE Chip Disable to Output in High Z
- 100 ns
tOHZ Output Disable to Output in High Z
- 100 ns
tOH Output Hold from Address Change
10 - ns
Notes: tCHZ, and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred
to output voltage levels.
(November, 1998, Version 2.1)
4 AMIC Technology, Inc.

5 Page
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A26E001AV diode, scr
Timing Waveforms (SRAM Selected continued)
Read Cycle 3 (1, 3, 4)
RAMCE
D OUT
tCLZ 5
tACE
A26E001A
tCHZ 5
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled, RAMCE = VIL.
3. Address valid prior to or coincident with RAMCE transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
Write Cycle 1(6)
(Write Enable Controlled)
Address
RAMCE
WE
D IN
D OUT
(4)
tAS1
tWC
tAW
tCW 5
tWP2
tWR 3
tDW
tWHZ 7
tDH
tOW 7
(November, 1998, Version 2.1)
8 AMIC Technology, Inc.

9 Page





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