93LCS56-ISN Datasheet PDF - Microchip Technology
Part Number | 93LCS56-ISN | |
Description | 2K/4K 2.5V Microwire Serial EEPROM with Software Write Protect | |
Manufacturers | Microchip Technology | |
Logo | ||
There is a preview and 93LCS56-ISN download ( pdf file ) link at the bottom of this page. Total 12 Pages |
Preview 1 page No Preview Available ! 93LC66A/B
4K 2.5V Microwire® Serial EEPROM
FEATURES
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current (typical)
- 1 µA standby current (maximum)
• 512 x 8 bit organization (93LC66A)
• 256 x 16 bit organization (93LC66B)
• Self-timed ERASE and WRITE cycles
(including auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial interface
• Device status signal during ERASE/WRITE cycles
• Sequential READ function
• 1,000,000 E/W cycles guaranteed
• Data retention > 200 years
• 8-pin PDIP/SOIC and 8-pin TSSOP packages
• Available for the following temperature ranges:
- Commercial (C):
- Industrial (I):
0°C to +70°C
-40°C to +85°C
PACKAGE TYPE
DIP
SOIC
BLOCK DIAGRAM
MEMORY
ARRAY
ADDRESS
DECODER
DI
CS
CLK
DATA
REGISTER
ADDRESS
COUNTER
OUTPUT
BUFFER
DO
MODE
DECODE
LOGIC
CLOCK
GENERATOR
Vcc
Vss
DESCRIPTION
The Microchip Technology Inc. 93LC66A/B are 4K-bit,
low voltage serial Electrically Erasable PROMs. The
device memory is configured as x8 (93LC66A) or
x16 bits (93LC66B). Advanced CMOS technology
makes these devices ideal for low power nonvolatile
memory applications. The 93LC66A/B is available in
standard 8-pin DIP, surface mount SOIC, and TSSOP
packages. The 93LC66AX/BX are only offered in a
150-mil SOIC package.
SOIC
TSSOP
CS 1
CLK 2
DI 3
DO 4
8 Vcc
CS
7 NC
CLK
6 NC
DI
5 Vss
DO
1
2
3
4
8 VCC
NC 1
7 NC
Vcc 2
6 NC
CS 3
5 Vss CLK 4
CS 1
8 NC CLK 2
DI 3
7 Vss
DO 4
6 DO
5 DI
8 Vcc
7 NC
6 NC
5 Vss
Microwire is a registered trademark of Motorola.
1998 Microchip Technology Inc.
DS21209C-page 1
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3.4 ERASE
The ERASE instruction forces all data bits of the spec-
ified address to the logical “1” state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical “0” indicates that program-
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
FIGURE 3-2: ERASE TIMING
CS
CLK
93LC66A/B
3.5 Erase All (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical “1” state. The ERAL cycle
is identical to the ERASE cycle except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS. Clocking of
the CLK pin is not necessary after the device has
entered the ERAL cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL) and before the entire ERAL cycle is com-
plete.
TCSL
CHECK STATUS
DI 1 1 1 AN AN-1 AN-2 ••• A0
HIGH-Z
DO
FIGURE 3-3: ERAL TIMING
CS
CLK
TCSL
TSV
BUSY
TWC
TCZ
READY
HIGH-Z
CHECK STATUS
DI
1
00
10
X •••
X
HIGH-Z
DO
Guaranteed at Vcc = 4.5V to +6.0V.
TSV
BUSY
TEC
TCZ
READY
HIGH-Z
1998 Microchip Technology Inc.
DS21209C-page 5
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for 93LCS56-ISN electronic component. |
Information | Total 12 Pages | |
Link URL | [ Copy URL to Clipboard ] | |
Download | [ 93LCS56-ISN.PDF Datasheet ] |
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