A80960HD32SL2GG Datasheet PDF - Intel Corporation
Part Number | A80960HD32SL2GG | |
Description | 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor | |
Manufacturers | Intel Corporation | |
Logo | ||
There is a preview and A80960HD32SL2GG download ( pdf file ) link at the bottom of this page. Total 70 Pages |
Preview 1 page No Preview Available ! 80960HA/HD/HT 32-Bit High-Performance
Superscalar Processor
Data Sheet
Advance Information
Product Features
s 32-Bit Parallel Architecture
—Load/Store Architecture
—Sixteen 32-Bit Global Registers
—Sixteen 32-Bit Local Registers
—1.28 Gbyte Internal Bandwidth
(80 MHz)
—On-Chip Register Cache
s Processor Core Clock
—80960HA is 1x Bus Clock
—80960HD is 2x Bus Clock
—80960HT is 3x Bus Clock
s Binary Compatible with Other 80960
Processors
s Issue Up To 150 Million Instructions per
Second
s High-Performance On-Chip Storage
—16 Kbyte Four-Way Set-Associative
Instruction Cache
—8 Kbyte Four-Way Set-Associative Data
Cache
—2 Kbyte General Purpose RAM
—Separate 128-Bit Internal Paths For
Instructions/Data
s 3.3 V Supply Voltage
—5 V Tolerant Inputs
—TTL Compatible Outputs
s Guarded Memory Unit
—Provides Memory Protection
—User/Supervisor Read/Write/Execute
s 32-Bit Demultiplexed Burst Bus
—Per-Byte Parity Generation/Checking
—Address Pipelining Option
—Fully Programmable Wait State
Generator
—Supports 8-, 16- or 32-Bit Bus Widths
—160 Mbyte/s External Bandwidth
(40 MHz)
s High-Speed Interrupt Controller
—Up to 240 External Interrupts
—31 Fully Programmable Priorities
—Separate, Non-maskable Interrupt Pin
s Dual On-Chip 32-Bit Timers
—Auto Reload Capability and One-Shot
—CLKIN Prescaling, ÷1, 2, 4 or 8
—JTAG Support - IEEE 1149.1 Compliant
Notice: This document contains information on products in the sampling and initial production
phases of development. The specifications are subject to change without notice. Verify with your
local Intel sales office that you have the latest datasheet before finalizing a design.
Order Number: 272495-007
July, 1998
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80960HA/HD/HT
Tables
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BOFF Functional Timing. BOFF occurs during a burst or
non-burst data cycle. .......................................................................................... 67
HOLD Functional Timing .................................................................................... 68
LOCK Delays HOLDA Timing ............................................................................ 69
FAIL Functional Timing....................................................................................... 69
A Summary of Aligned and Unaligned Transfers for 32-Bit Regions ................. 70
A Summary of Aligned and Unaligned Transfers for 16-Bit Bus ........................ 72
A Summary of Aligned and Unaligned Transfers for 8-Bit Bus .......................... 73
Idle Bus Operation.............................................................................................. 74
Bus States .......................................................................................................... 75
80960Hx Product Description................................................................................ 1
Fail Codes For BIST (bit 7 = 1) ............................................................................. 4
Remaining Fail Codes (bit 7 = 0)........................................................................... 4
80960Hx Instruction Set ........................................................................................ 5
80960HA/HD/HT Package Types and Speeds ..................................................... 6
Pin Description Nomenclature............................................................................... 7
80960Hx Processor Family Pin Descriptions ........................................................ 8
80960Hx 168-Pin PGA Pinout — Signal Name Order ........................................14
80960Hx 168-Pin PGA Pinout — Pin Number Order ..........................................16
80960Hx PQ4 Pinout — Signal Name Order ......................................................19
80960Hx PQ4 Pinout — Pin Number Order........................................................21
Maximum TA at Various Airflows in °C (PGA Package Only)..............................24
80960Hx 168-Pin PGA Package Thermal Characteristics ..................................24
Maximum TA at Various Airflows in °C (PQ4 Package Only) ..............................25
80960Hx 208-Pin PQ4 Package Thermal Characteristics ..................................25
Fields of 80960Hx Device ID...............................................................................27
80960Hx Device ID Model Types........................................................................27
Device ID Version Numbers for Different Steppings ...........................................27
Operating Conditions...........................................................................................29
VDIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V)...............30
80960Hx DC Characteristics ...............................................................................32
80960Hx AC Characteristics ...............................................................................34
AC Characteristics Notes ....................................................................................36
80960Hx Boundary Scan Test Signal Timings....................................................36
80960Hx Boundary Scan Chain ..........................................................................76
Data Sheet Version -006 to -007 Revision History..............................................96
Advance Information Datasheet
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