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PDF AD7467 Data sheet ( Hoja de datos )
| Número de pieza | AD7467 | |
| Descripción | 1.8 V/ Micro-Power/ 8/10/12-Bit ADCs in 6 Lead SOT-23 | |
| Fabricantes | Analog Devices | |
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a
pecifications
1.8 V, Micro-Power,
8/10/12-Bit ADCs in 6 Lead SOT-23
Preliminary Technical Data
AD7466/AD7467/AD7468
FEATURES
Specified for VDD of 1.8 V to 3.6 V
Low Power:
0.9 mW max at 60 kSPS with 3.6 V Supplies
0.4 mW max at 100 kSPS with 1.8 V Supplies
Fast Throughput Rate: 100 kSPS
Wide Input Bandwidth:
70dB SNR at 30 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface
SPI/QSPI/µWire/DSP Compatible
Standby Mode: 0.5 µA max
6-Lead SOT-23 Package and 8 lead µSOIC
APPLICATIONS
Battery Powered Systems
Medical Instruments
Ramote Data Acquisition
Isolated Data Acquisition
GENERAL DESCRIPTION
The AD7466/AD7467/AD7468 are 12/10/8-bit, high
speed, low power, successive-approximation ADCs re-
spectively. The parts operate from a single 1.8 V to 3.6 V
power supply and feature throughput rates up to 100
kSPS. The parts contain a low-noise, wide bandwidth
track/hold amplifier which can handle input frequencies in
excess of 100 kHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to
interface with microprocessors or DSPs. The input signal
is sampled on the falling edge of CS and the conversion is
also initiated at this point. There are no pipelined delays
associated with the part.
The AD7466/AD7467/AD7468 use advanced design tech-
niques to achieve very low power dissipation at high
throughput rates.
The reference for the part is taken internally from VDD.
This allows the widest dynamic input range to the ADC.
Thus the analog input range for the part is 0 to VDD. The
conversion rate is determined by the SCLK.
FUNCTIONAL BLOCK DIAGRAM
VDD
12/10/8-BIT
VIN T/H SUCCESSIVE
APPROXIMATION
ADC
CONTROL LOGIC
AD7466/67/68
GND
SCLK
SDATA
CS
PRODUCT HIGHLIGHTS
1. Specified for Supply voltages of 1.8 V to 3.6 V
2. 8/10/12-Bit ADCs in a SOT-23 package.
3. High Throughput with Low Power Consumption
4. Flexible Power/Serial Clock Speed Management
The conversion rate is determined by the serial clock
allowing the conversion time to be reduced through the
serial clock speed increase. Automatic power down after
conversion, which allows the average power cunsumption
to be reduced when in powerdown. Power consumption
is 0.5 µA max when in powerdown.
5. Reference derived from the power supply.
6. No Pipeline Delay
The part features a standard successive-approximation
ADC with accurate control of the conversions via a CS
input.
REV. PrC 07/01
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2001
1 page  
pecifications
AD7466/AD7467/AD7468
TIMING SPECIFICATIONS1 (VDD = +1.8 V to +3.6 V; TA = TMIN to TMAX, unless otherwise noted.)
Parameter AD7466
Units
Description
fSCLK 2
tCONVERT
tquiet
t1
t2
t33
t43
t5
t6
t7
t84
tpower-up5
10
TBD
16* tSCLK
TBD
TBD
10
TBD
TBD
0.4tSCLK
0.4tSCLK
TBD
TBD
TBD
kHz min
MHz max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
µs typ
Minimum Quiet Time required between Bus Relinquish
and start of next conversion
Minimum CS Pulse Width
CS to SCLK Setup Time
Delay from CS Until SDATA 3-State Disabled
Data Access Time After SCLK Falling Edge
SCLK Low Pulse Width
SCLK High Pulse Width
SCLK to Data Valid Hold Time
SCLK falling Edge to SDATA High Impedance
Power up time from Full Power-down.
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 Volts.
2Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to
remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the
part and is independent of the bus loading.
5See Power-up Time section.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
VDD to GND
Analog Input Voltage to GND
Digital Input Voltage to GND
–0.3 V to TBD V
–0.3 V to VDD + 0.3 V
–0.3 V to TBDV
Digital Output Voltage to GND –0.3 V to VDD + 0.3 V
Input Current to Any Pin Except Supplies2
±10 mA
Operating Temperature Range
Commercial (A, B Version)
–40°C to +85°C
Storage Temperature Range
–65°C to +150°C
Junction Temperature
+150°C
SOT-23 Package, Power Dissipation
450 mW
θJA Thermal Impedance
229.6°C/W (SOT23)
205.9°C/W (µSOIC)
θJC Thermal Impedance
91.99°C/W (SOT23)
43.74°C/W (µSOIC)
Lead Temperature, Soldering
Vapor Phase (60 secs)
+215°C
Infared (15 secs)
+220°C
ESD
TBD
200µA
IO L
TO
OUTPUT
PIN
CL
50pF
200µA
IO H
+1.6V
Figure 1. Load Circuit for Digital Output Timing
Specifications
NOTES
1Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch up.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7466/AD7467/AD7468 feature proprietary ESD protection circuitry, per-
manent damage may occur on devices subjected to high energy electrostatic discharges. There-
fore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
REV. PrC
–5–
5 Page 
pecifications
AD7466/AD7467/AD7468
0
0
0
0000000
TITLE
Figure 13. THD vs. Analog Input Frequency for Various
Source Impedance
Digital Inputs
The digital inputs applied to the AD7466/AD7467/
AD7468 are not limited by the maximum ratings which
limit the analog inputs. One advantage of SCLK and CS
not being restricted by the VDD + 0.3V limit is the fact that
power supply sequencing issues are avoided. If CS or
SCLK are applied before VDD then there is no risk of
latch-up as there would be on the analog inputs if a signal
greater than 0.3V was applied prior to VDD.
MODE OF OPERATION
The AD7466/AD7467/AD7468 automatically enters
powerdown at the end of each conversion. This mode of
operation is designed to provide flexible power manage-
ment options and to optimize the power dissipation/
throughput rate ratio for differing application require-
ments. Figure 14 shows the general diagram of the
operaion of the AD7466/AD7467/AD7468. On the falling
CS edge the part begins to power up and the Track and
Hold, which was in Hold while the part was in power
down, will go into track mode. When operating the part
with a 2.4 MHz clock it will take 2 clock cycles to fully
power up the part and acquire the input signal. On the
third SCLK falling edge after the CS falling edge the
Track and Hold will return to hold mode. For the
AD7466 sixteen serial clock cycles are required to com-
plete the conversion and access the complete conversion
result.On the 16th SCLK falling edge the part will auto-
matically enter power down . The AD7467 will automati-
cally enter powerdown on the fourteenth SCLK falling
edge. The AD7468 will automatically enter powerdown
on the twelveth SCLK falling edge. When supplies are
first applied to the AD7466/AD7467/AD7468 a dummy
conversion should be performed to ensure that the part is
in powerdown mode.
The conversion is iniated on the falling edge of CS as
described in the Serial Interface section. For the AD7466
if CS is brought high any time before the 16th SCLK
falling edge the part will enter power down and the con-
version that was initiated by the falling edge of CS will be
terminated and SDATA will go back into tri-state. This
also applies for the AD7467/AD7468, if CS is brought
high before the conversion is complete (the 14th SCLK
falling edge for the AD7467, and the 12th SCLK falling
edge for the AD7468) the part will enter powerdown and
the conversion will be terminated.
Once a data transfer is complete (SDATA has returned to
tri-state), another conversion can be initiated after the
quiet time, tquiet, has elapsed by bringing CS low again.
REV. PrC
THE PART BEGINS
TO POWER UP
123
AD7468 ENTERS AD7467 ENTERS
POWERDOWN POWERDOWN AD7466 ENTERS
POWERDOWN
12 14 16
VALID DATA
Figure 14. Normal Mode Operation
–11–
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet AD7467.PDF ] | |
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