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PDF AD73422 Data sheet ( Hoja de datos )
| Número de pieza | AD73422 | |
| Descripción | Dual Low Power CMOS Analog Front End with DSP Microcomputer | |
| Fabricantes | Analog Devices | |
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a Dual Low Power CMOS
Analog Front End with DSP Microcomputer
AD73422
FEATURES
AFE PERFORMANCE
Two 16-Bit A/D Converters
Two 16-Bit D/A Converters
Programmable Input/Output Sample Rates
78 dB ADC SNR
77 dB DAC SNR
64 kS/s Maximum Sample Rate
–90 dB Crosstalk
Low Group Delay (25 s Typ per ADC Channel,
50 s Typ per DAC Channel)
Programmable Input/Output Gain
On-Chip Reference
DSP PERFORMANCE
19 ns Instruction Cycle Time @ 3.3 V, 52 MIPS
Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 400 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
GENERAL DESCRIPTION
The AD73422 is a single device incorporating a dual analog
front end and a microcomputer optimized for digital signal
processing (DSP) and other high speed numeric processing
applications.
The AD73422’s analog front end (AFE) section features a dual
front-end converter for general purpose applications including
speech and telephony. The AFE section features two 16-bit A/D
conversion channels and two 16-bit D/A conversion channels.
Each channel provides 77 dB signal-to-noise ratio over a
voiceband signal bandwidth. It also features an input-to-output
gain network in both the analog and digital domains. This is
featured on both codecs and can be used for impedance match-
ing or scaling when interfacing to Subscriber Line Interface
Circuits (SLICs).
The AD73422 is particularly suitable for a variety of applica-
tions in the speech and telephony area including low bit rate,
high quality compression, speech enhancement, recognition
and synthesis. The low group delay characteristic of the AFE
makes it suitable for single or multichannel active control
FUNCTIONAL BLOCK DIAGRAM
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
POWER-DOWN
CONTROL
MEMORY
16K PM 16K DM
(OPTIONAL (OPTIONAL
8K) 8K)
FULL MEMORY
MODE
PROGRAMMABLE
I/O
AND
FLAGS
EXTERNAL
ADDRESS
BUS
PROGRAM MEMORY ADDRESS
EXTERNAL
DATA
BUS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
ADSP-2100 BASE
ARCHITECTURE
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
BYTE DMA
CONTROLLER
OR
EXTERNAL
DATA
BUS
INTERNAL
DMA
PORT
HOST MODE
REF
SERIAL PORT
SPORT 2
ADC1 DAC1
ADC2 DAC2
ANALOG FRONT END
SECTION
applications. The A/D and D/A conversion channels feature
programmable input/output gains with ranges 38 dB and 21 dB
respectively. An on-chip reference voltage is included to allow
single supply operation.
The sampling rate of the AFE is programmable with four sepa-
rate settings offering 64, 32, 16 and 8 kHz sampling rates (from
a master clock of 16.384 MHz), while the serial port (SPORT2)
allows easy expansion of the number of I/O channels by cascad-
ing extra AFEs external to the AD73422.
The AD73422’s DSP engine combines the ADSP-2100 family
base architecture (three computational units, data address gen-
erators and a program sequencer) with two serial ports, a 16-bit
internal DMA port, a byte DMA port, a programmable timer,
Flag I/O, extensive interrupt capabilities and on-chip program
and data memory.
The AD73422-80 integrates 80K bytes of on-chip memory
configured as 16K words (24-bit) of program RAM, and 16K
words (16-bit) of data RAM. The AD73422-40 integrates 40K
bytes of on-chip memory configured as 8K words (24-bit) of
program RAM, and 8K words (16-bit) of data RAM. Power-
down circuitry is also provided to meet the low power needs of
battery operated portable equipment. The AD73422 is available
in a 119-ball PBGA package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1 page  
AD73422
POWER CONSUMPTION
Conditions
Typ Max
SE
AFE SECTION
ADCs Only On
DACs Only On
ADCs and DACs On
ADCs and DACs
and Input Amps On
ADCs and DACs
and AGT On
All Sections On
REFCAP Only On
REFCAP and
REFOUT Only On
All AFE Sections Off
All AFE Sections Off
11.5
20
24.5
30
29
37
0.8
3.5
1.5
10 µA
12
22
27
34
32.5
43.5
1.25
4.75
3.0
40 µA
1
1
1
1
1
1
0
0
0
0
NOTES
The above values are in mA and are typical values unless otherwise noted.
Specifications subject to change without notice.
AMCLK On Test Conditions
YES REFOUT Disabled
YES REFOUT Disabled
YES REFOUT Disabled
YES REFOUT Disabled
YES REFOUT Disabled
YES
NO REFOUT Disabled
NO
YES AMCLK Active Levels Equal to 0 V and DVDD
NO Digital Inputs Static and Equal to 0 V or DVDD
TIMING CHARACTERISTICS–AFE SECTION1
Parameter
Limit
Units
Description
Clock Signals
t1
t2
t3
Serial Port
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
61
24.4
24.4
t1
0.4 × t1
0.4 × t1
20
0
10
10
10
10
30
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns max
See Figure 1
16.384 MHz AMCLK Period
AMCLK Width High
AMCLK Width Low
See Figures 3 and 4
SCLK Period (SCLK = AMCLK)
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup Before SCLK Low
SDI/SDIFS Hold After SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold After SCLK High
SDO Hold After SCLK High
SDO Delay from SCLK High
SCLK Delay from AMCLK
NOTES
1For details of the DSP section timing, please refer to the ADSP-2185L data sheet and the ADSP-2100 Family User’s Manual, Third Edition.
Specifications subject to change without notice.
REV. 0
–5–
5 Page 
Table I. PGA Settings for the Encoder Channel
IGS2
0
0
0
0
1
1
1
1
IGS1
0
0
1
1
0
0
1
1
IGS0
0
1
0
1
0
1
0
1
Gain (dB)
0
6
12
18
20
26
32
38
ADC
Both ADCs consist of an analog sigma-delta modulator and a
digital antialiasing decimation filter. The sigma-delta modu-
lator noise-shapes the signal and produces 1-bit samples at a
DMCLK/8 rate. This bitstream, representing the analog input
signal, is input to the antialiasing decimation filter. The decima-
tion filter reduces the sample rate and increases the resolution.
Analog Sigma-Delta Modulator
The AD73422’s input channels employ a sigma-delta conver-
sion technique, which provides a high resolution 16-bit output
with system filtering being implemented on-chip.
Sigma-delta converters employ a technique known as over-
sampling where the sampling rate is many times the highest
frequency of interest. In the case of the AD73422, the initial
sampling rate of the sigma-delta modulator is DMCLK/8. The
main effect of oversampling is that the quantization noise is
spread over a very wide bandwidth, up to FS/2 = DMCLK/16
(Figure 4a). This means that the noise in the band of interest is
much reduced. Another complementary feature of sigma-delta
converters is the use of a technique called noise-shaping. This
technique has the effect of pushing the noise from the band of
interest to an out-of-band position (Figure 4b). The combination
AD73422
of these techniques, followed by the application of a digital
filter, sufficiently reduces the noise in band to ensure good
dynamic performance from the part (Figure 4c).
Figure 5 shows the various stages of filtering that are employed
in a typical AD73422 application. In Figure 5a we see the trans-
fer function of the external analog antialias filter. Even though it
is a single RC pole, its cutoff frequency is sufficiently far away
from the initial sampling frequency (DMCLK/8) that it takes
care of any signals that could be aliased by the sampling fre-
quency. This also shows the major difference between the initial
oversampling rate and the bandwidth of interest. In Figure 5b,
the signal and noise-shaping responses of the sigma-delta modu-
lator are shown. The signal response provides further rejection
of any high frequency signals, while the noise-shaping will push
the inherent quantization noise to an out-of-band position. The
detail of Figure 5c shows the response of the digital decima-
tion filter (Sinc-cubed response) with nulls every multiple of
DMCLK/256, which corresponds to the decimation filter up-
date rate for a 64 kHz sampling. The nulls of the Sinc3 response
correspond with multiples of the chosen sampling frequency.
The final detail in Figure 5d shows the application of a final
antialias filter in the DSP engine. This has the advantage of
being implemented according to the user’s requirements and
available MIPS. The filtering in Figures 5a through 5c is imple-
mented in the AD73422.
FB = 4kHz
FSINIT = DMCLK/8
a. Analog Antialias Filter Transfer Function
SIGNAL TRANSFER FUNCTION
BAND
OF
INTEREST
a.
FS /2
DMCLK/16
NOISE TRANSFER FUNCTION
FB = 4kHz
FSINIT = DMCLK/8
b. Analog Sigma-Delta Modulator Transfer Function
NOISE-SHAPING
BAND
OF
INTEREST
b.
FS /2
DMCLK/16
DIGITAL FILTER
BAND
OF
INTEREST
c.
FS /2
DMCLK/16
Figure 4. Sigma-Delta Noise Reduction
REV. 0
–11–
FB = 4kHz
FSINTER = DMCLK/256
c. Digital Decimator Transfer Function
FB = 4kHz FSFINAL = 8kHz FSINTER = DMCLK/256
d. Final Filter LPF (HPF) Transfer Function
Figure 5. ADC Frequency Responses
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