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PDF AD669 Data sheet ( Hoja de datos )
| Número de pieza | AD669 | |
| Descripción | Monolithic 16-Bit DACPORT | |
| Fabricantes | Analog Devices | |
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a
Monolithic 16-Bit
DACPORT
AD669
FEATURES
Complete 16-Bit D/A Function
On-Chip Output Amplifier
High Stability Buried Zener Reference
Monolithic BiMOS II Construction
؎1 LSB Integral Linearity Error
15-Bit Monotonic over Temperature
Microprocessor Compatible
16-Bit Parallel Input
Double-Buffered Latches
Fast 40 ns Write Pulse
Unipolar or Bipolar Output
Low Glitch: 15 nV-s
Low THD+N: 0.009%
MIL-STD-883 Compliant Versions Available
GENERAL DESCRIPTION
The AD669 DACPORT® is a complete 16-bit monolithic D/A
converter with an on-board reference and output amplifier. It is
manufactured on Analog Devices’ BiMOS II process. This pro-
cess allows the fabrication of low power CMOS logic functions
on the same chip as high precision bipolar linear circuitry. The
AD669 chip includes current switches, decoding logic, an output
amplifier, a buried Zener reference and double-buffered latches.
The AD669’s architecture insures 15-bit monotonicity over
temperature. Integral nonlinearity is maintained at ± 0.003%,
while differential nonlinearity is ± 0.003% max. The on-chip
output amplifier provides a voltage output settling time of 10 µs
to within 1/2 LSB for a full-scale step.
Data is loaded into the AD669 in a parallel 16-bit format. The
double-buffered latch structure eliminates data skew errors and
provides for simultaneous updating of DACs in a multi-DAC
system. Three TTL/LSTTL/5 V CMOS compatible signals con-
trol the latches: CS, L1 and LDAC.
The output range of the AD669 is pin programmable and can
be set to provide a unipolar output range of 0 V to +10 V or a
bipolar output range of –10 V to +10 V.
The AD669 is available in seven grades: AN and BN versions
are specified from –40°C to +85°C and are packaged in a 28-pin
plastic DIP. The AR and BR versions are specified for –40°C to
+85°C operation and are packaged in a 28-pin SOIC. The SQ
version is specified from –55°C to +125°C and is packaged in a
hermetic 28-pin cerdip package. The AD669 is also available
compliant to MIL-STD-883. Refer to the AD669/883B data
sheet for specifications and test conditions.
DACPORT is a registered trademark of Analog Devices, Inc.
FUNCTIONAL BLOCK DIAGRAM
(MSB)
DB15
7
(LSB)
DB0
22
CS 6
L1 5
LDAC 23
REF IN 27
10k
16-BIT LATCH
16-BIT LATCH
16-BIT DAC
REF OUT 28
10V REF
AD669
10k
10.05k
26 SPAN/
BIP OFF
AMP
25 VOUT
24 AGND
1
–VEE
2
+VCC
3
+VLL
4
DGND
PRODUCT HIGHLIGHTS
1. The AD669 is a complete voltage output 16-bit DAC with
voltage reference and digital latches on a single IC chip.
2. The internal buried Zener reference is laser trimmed to
10.000 volts with a ± 0.2% maximum error. The reference
voltage is also available for external applications.
3. The AD669 is both dc and ac specified. DC specs include
± 1 LSB INL error and ± 1 LSB DNL error. AC specs include
0.009% THD+ N and 83 dB SNR. The ac specifications
make the AD669 suitable for signal generation applications.
4. The double-buffered latches on the AD669 eliminate data
skew errors while allowing simultaneous updating of DACs in
multi-DAC systems.
5. The output range is a pin-programmable unipolar 0 V to
+10 V or bipolar –10 V to +10 V output. No external compo-
nents are necessary to set the desired output range.
6. The AD669 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD669/883B data sheet for detailed
specifications.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD669
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY: Analog Devices defines inte-
gral nonlinearity as the maximum deviation of the actual, ad-
justed DAC output from the ideal analog output (a straight line
drawn from 0 to FS–1 LSB) for any bit combination. This is
also referred to as relative accuracy.
DIFFERENTIAL NONLINEARITY: Differential nonlinearity
is the measure of the change in the analog output, normalized to
full scale, associated with a 1 LSB change in the digital input
code. Monotonic behavior requires that the differential linearity
error be within ± 1 LSB over the temperature range of interest.
MONOTONICITY: A DAC is monotonic if the output either
increases or remains constant for increasing digital inputs with
the result that the output will always be a single-valued function
of the input.
GAIN ERROR: Gain error is a measure of the output error be-
tween an ideal DAC and the actual device output with all 1s
loaded after offset error has been adjusted out.
OFFSET ERROR: Offset error is a combination of the offset
errors of the voltage-mode DAC and the output amplifier and is
measured with all 0s loaded in the DAC.
BIPOLAR ZERO ERROR: When the AD669 is connected for
bipolar output and 10 . . . 000 is loaded in the DAC, the devia-
tion of the analog output from the ideal midscale value of 0 V is
called the bipolar zero error.
DRIFT: Drift is the change in a parameter (such as gain, offset
and bipolar zero) over a specified temperature range. The drift
temperature coefficient, specified in ppm/°C, is calculated by
measuring the parameter at TMIN, 25°C and TMAX and dividing
the change in the parameter by the corresponding temperature
change.
TOTAL HARMONIC DISTORTION + NOISE: Total har-
monic distortion + noise (THD+N) is defined as the ratio of the
square root of the sum of the squares of the values of the har-
monics and noise to the value of the fundamental input fre-
quency. It is usually expressed in percent (%).
THD+N is a measure of the magnitude and distribution of lin-
earity error, differential linearity error, quantization error and
noise. The distribution of these errors may be different, depend-
ing upon the amplitude of the output signal. Therefore, to be
the most useful, THD+N should be specified for both large and
small signal amplitudes.
SIGNAL-TO-NOISE RATIO: The signal-to-noise ratio is de-
fined as the ratio of the amplitude of the output when a full-
scale signal is present to the output with no signal present. This
is measured in dB.
DIGITAL-TO-ANALOG GLITCH IMPULSE: This is the
amount of charge injected from the digital inputs to the analog
output when the inputs change state. This is measured at half
scale when the DAC switches around the MSB and as many
as possible switches change state, i.e., from 011 . . . 111 to
100 . . . 000.
DIGITAL FEEDTHROUGH: When the DAC is not selected
(i.e., CS is held high), high frequency logic activity on the digi-
tal inputs is capacitively coupled through the device to show up
as noise on the VOUT pin. This noise is digital feedthrough.
THEORY OF OPERATION
The AD669 uses an array of bipolar current sources with MOS
current steering switches to develop a current proportional to
the applied digital word, ranging from 0 mA to 2 mA. A seg-
mented architecture is used, where the most significant four
data bits are thermometer decoded to drive 15 equal current
sources. The lesser bits are scaled using a R-2R ladder, then ap-
plied together with the segmented sources to the summing node
of the output amplifier. The internal span/bipolar offset resistor
can be connected to the DAC output to provide a 0 V to +10 V
span, or it can be connected to the reference input to provide a
–10 V to +10 V span.
(MSB)
DB15
7
(LSB)
DB0
22
CS 6
L1 5
LDAC 23
10k
REF IN 27
16-BIT LATCH
16-BIT LATCH
16-BIT DAC
REF OUT 28
10V REF
AD669
10k
10.05k
26 SPAN/
BIP OFF
AMP
25 VOUT
24 AGND
1
–VEE
2
+VCC
3
+VLL
4
DGND
Figure 2. AD669 Functional Block Diagram
ANALOG CIRCUIT CONNECTIONS
Internal scaling resistors provided in the AD669 may be con-
nected to produce a unipolar output range of 0 V to +10 V or a
bipolar output range of –10 V to +10 V. Gain and offset drift
are minimized in the AD669 because of the thermal tracking of
the scaling resistors with other device components.
UNIPOLAR CONFIGURATION
The configuration shown in Figure 3a will provide a unipolar
0 V to +10 V output range. In this mode, 50 Ω resistors are tied
between the span/bipolar offset terminal (Pin 26) and VOUT (Pin
25), and between REF OUT (Pin 28) and REF IN (Pin 27). It
is possible to use the AD669 without any external components
by tying Pin 28 directly to Pin 27 and Pin 26 directly to Pin 25.
Eliminating these resistors will increase the gain error by 0.25%
of FSR.
(MSB)
DB15
7
(LSB)
DB0
22
CS 6
L1 5
LDAC 23
16-BIT LATCH
16-BIT LATCH
10k
27 16-BIT DAC
R1
50Ω 28
10V REF
AD669
10k
26
10.05k
R2
50Ω
AMP
25
OUTPUT
24 GND
1
–VEE
2
+VCC
3
+VLL
4
REV. A
Figure 3a. 0 V to +10 V Unipolar Voltage Output
–5–
5 Page 
NOISE
In high resolution systems, noise is often the limiting factor. A
16-bit DAC with a 10 volt span has an LSB size of 153 µV
(–96 dB). Therefore, the noise floor must remain below this
level in the frequency range of interest. The AD669’s noise
spectral density is shown in Figures 12 and 13. Figure 12 shows
the DAC output noise voltage spectral density for a 20 V span
excluding the reference. This figure shows the l/f corner frequency
at 100 Hz and the wideband noise to be below 120 nV/√Hz.
Figure 13 shows the reference noise voltage spectral density.
This figure shows the reference wideband noise to be below
125 nV/√Hz.
1000
100
10
1
1 10 100 1k 10k 100k 1M 10M
FREQUENCY – Hz
Figure 12. DAC Output Noise Voltage Spectral Density
1000
100
10
1
1 10 100 1k 10k 100k 1M 10M
FREQUENCY – Hz
Figure 13. Reference Noise Voltage Spectral Density
BOARD LAYOUT
Designing with high resolution data converters requires careful
attention to board layout. Trace impedance is the first issue. A
306 µA current through a 0.5 Ω trace will develop a voltage
drop of 153 µV, which is 1 LSB at the 16-bit level for a 10 V
full-scale span. In addition to ground drops, inductive and ca-
pacitive coupling need to be considered, especially when high
accuracy analog signals share the same board with digital sig-
nals. Finally, power supplies need to be decoupled in order to
filter out ac noise.
AD669
Analog and digital signals should not share a common path.
Each signal should have an appropriate analog or digital return
routed close to it. Using this approach, signal loops enclose a
small area, minimizing the inductive coupling of noise. Wide PC
tracks, large gauge wire, and ground planes are highly recom-
mended to provide low impedance signal paths. Separate analog
and digital ground planes should also be utilized, with a single
interconnection point to minimize ground loops. Analog signals
should be routed as far as possible from digital signals and
should cross them at right angles.
One feature that the AD669 incorporates to help the user layout
is the analog pins (VCC, VEE, REF OUT, REF IN, SPAN/BIP
OFFSET, VOUT and AGND) are adjacent to help isolate analog
signals from digital signals.
SUPPLY DECOUPLING
The AD669 power supplies should be well filtered, well regu-
lated, and free from high frequency noise. Switching power sup-
plies are not recommended due to their tendency to generate
spikes which can induce noise in the analog system.
Decoupling capacitors should be used in very close layout prox-
imity between all power supply pins and ground. A 10 µF tanta-
lum capacitor in parallel with a 0.1 µF ceramic capacitor
provides adequate decoupling. VCC and VEE should be bypassed
to analog ground, while VLL should be decoupled to digital
ground.
An effort should be made to minimize the trace length between
the capacitor leads and the respective converter power supply
and common pins. The circuit layout should attempt to locate
the AD669, associated analog circuitry and interconnections as
far as possible from logic circuitry. A solid analog ground plane
around the AD669 will isolate large switching ground currents.
For these reasons, the use of wire wrap circuit construction
is not recommended; careful printed circuit construction is
preferred.
GROUNDING
The AD669 has two pins, designated analog ground (AGND)
and digital ground (DGND.) The analog ground pin is the
“high quality” ground reference point for the device. Any exter-
nal loads on the output of the AD669 should be returned to
analog ground. If an external reference is used, this should also
be returned to the analog ground.
If a single AD669 is used with separate analog and digital
ground planes, connect the analog ground plane to AGND and
the digital ground plane to DGND keeping lead lengths as short
as possible. Then connect AGND and DGND together at the
AD669. If multiple AD669s are used or the AD669 shares ana-
log supplies with other components, connect the analog and
digital returns together once at the power supplies rather than at
each chip. This single interconnection of grounds prevents large
ground loops and consequently prevents digital currents from
flowing through the analog ground.
REV. A
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD669.PDF ] | |
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