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PDF AD8303 Data sheet ( Hoja de datos )
| Número de pieza | AD8303 | |
| Descripción | +3 V/ Dual/ Serial Input Complete 12-Bit DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Complete Dual 12-Bit DAC
Pretrimmed Internal Voltage Reference
Single +3 V Operation
0.5 mV/Bit with 2.0475 V Full Scale
Low Power: 9.6 mW
3-Wire Serial SPI Compatible Interface
Power Shutdown IDD < 1 A
Compact SO-14, 1.75 mm Height Package
APPLICATIONS
Portable Communications
Digitally Controlled Calibration
Servo Controls
PC Peripherals
+3 V, Dual, Serial Input
Complete 12-Bit DAC
AD8303
CS
CLK
SDI
(DATA)
LDA
LDB
FUNCTIONAL BLOCK DIAGRAM
VDD
En
R
SE
HG
II
FS
TT
E
R
R
E
DG
AI
CS
A
T
E
DR
PR
R
DE
DG
AI
CS
B
T
E
R
PR
DAC A
OP
AMP
A
R
BE
AF
REF
BUF
NE
DR
GE
AN
PC
E
REF
BUF
DAC B
OP
AMP
B
AD8303
VOUTA
VREF
VOUTB
DGND MSB RS
AGND
SHDN
GENERAL DESCRIPTION
The AD8303 is a complete (includes internal reference) dual,
12-bit, voltage output digital-to-analog converter designed to
operate from a single +3 volt supply. Built using a CBCMOS
process, this monolithic DAC offers the user low cost and ease-
of-use in single-supply +3 volt systems. Operation is guaranteed
over the supply voltage range of +2.7 V to +5.5 V making this
device ideal for battery operated applications.
The 2.0475 V full-scale voltage output is laser-trimmed to
maintain accuracy over the operating temperature range of the
device. The binary input data format provides an easy-to-use
one-half millivolt-per-bit software programmability. The voltage
outputs are capable of sourcing 3 mA.
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
VDD = +5V
TA = –40°C, +25°C, +85°C
1024
2048
3072
4096
DIGITAL INPUT CODE – Decimal
A double buffered serial data interface offers high speed, three-
wire, DSP and SPI microcontroller compatible inputs using
data in (SDI), clock (CLK) and load strobe (LDA + LDB)
pins. A chip-select (CS) pin simplifies connection of multiple
DAC packages by enabling the clock input when active low.
Additionally, an RS input sets the output to zero scale or to 1/2
scale based on the level applied to the MSB pin. A power
shutdown feature reduces power dissipation to less than 3 µW.
The AD8303 is specified over the extended industrial (–40°C to
+85°C) temperature range. AD8303s are available in plastic
DIP and low profile 1.75 mm height SO-14 surface mount
packages. For single-channel DAC applications, see the
AD8300 which is offered in the 8-lead DIP and SO-8 packages.
2
1.5
1
0.5
0
–0.5
–1
–1.5
–2
0
–40°C
VDD = +5V
+25°C
+85°C
1024
2048
3072
4096
DIGITAL INPUT CODE – Decimal
Figure 1. Differential Nonlinearity Error vs. Code
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Figure 2. Linearity Error vs. Digital Code and Temperature
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD8303
Table I. Control-Logic Truth Table
CS CLK RS MSB SHDN LDA/B Serial Shift Register Function
DAC Register Function
HX
LL
LH
L ↑+
↑+ L
HX
HX
XX
XX
XX
XX
XX
HX
HX
HX
HX
HX
HX
HX
LH
↑+ H
LL
↑+ X
XX
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
↓–
L
X
H
X
H
X
No Effect
No Effect
No Effect
Shift-Register-Data Advanced One Bit
No Effect
No Effect
No Effect
No Effect
No Effect
No Effect
No Effect
No Effect
Latched
Latched
Latched
Latched
Latched
Updated with Current Shift Register Contents
Transparent
Loaded with 800H
Latched with 800H
Loaded with All Zeros
Latched All Zeros
No Effect
NOTES
1↑+ positive logic transition; ↓– negative logic transition; X Don’t Care.
2Do not clock in serial data while LDA or LDB is LOW.
Pin No. Name
Function
PIN DESCRIPTIONS
1
AGND
Analog Ground.
2
VOUTA
DAC voltage output, 2.0475 V full scale with 0.5 mV per bit. An internal temperature stabilized reference
maintains a fixed full-scale voltage independent of time, temperature and power supply variations.
3
VREF
Reference Voltage Output Terminal. Very high output resistance must be buffered if used as a virtual
ground.
4 DGND Digital Ground
5 CS Chip Select, Active Low Input. Disables shift register loading when high. Does not effect LDA or LDB
operation.
6
CLK
Clock Input, positive edge clocks data into shift register.
7 SDI Serial Data Input, input data loads directly into the shift register.
8
LDA
Load DAC register strobes, active low. Transfers shift register data to DAC A register. Asynchronous active
low input. See Control Logic Truth Table for operation.
9 RS Resets DAC register to zero condition or half-scale depending on MSB pin. Asynchronous active low input.
10
LDB
Load DAC register strobes, active low. Transfers shift register data to DAC B register. Asynchronous active
low input. See Control Logic Truth Table for operation.
11
MSB
Digital Input: Logic High presets DAC registers to half-scale 800H (sets MSB bit to one) when the RS pin
is strobed; Logic Low clears all DAC registers to zero (000H) when the RS pin is strobed.
12
SHDN
Active low shutdown control input. Does not affect register contents as long as power is present on VDD.
13 VDD Positive power supply input. Specified range of operation +2.7 V to +5.5 V
14
VOUTB
DAC voltage output, 2.0475 V full scale with 0.5 mV per bit. An internal temperature stabilized reference
maintains a fixed full-scale voltage independent of time, temperature and power supply variations.
PIN CONFIGURATION
14-Pin P-DIP (N-14)
14-Lead SOIC (R-14)
AGND 1
14 VOUTB
VOUTA 2
13 VDD
VREF 3 AD8303 12 SHDN
DGND 4 TOP VIEW 11 MSB
(Not to Scale)
CS 5
10 LDB
CLK 6
9 RS
SDI 7
8 LDA
REV. 0
–5–
5 Page 
SHUTDOWN (SHDN)
The shutdown feature is activated when SHDN is pulled low.
While the AD8303 is in shutdown mode, the voltage reference,
DACs, and output amplifiers are all turned off. Supply current
is less than 1 µA. The DAC output voltage goes to 0 V, pulled
to GND by the 12.5 kΩ feedback resistors (Figure 22).
If power (i.e., VDD) is maintained to the AD8303 during
shutdown, the value stored in the DAC input latches will not
change. When the SHDN pin is driven high, the DACs will
return to the same voltages as before shutdown. The CMOS
logic section of the AD8303 remains active while SHDN is low.
Thus, new data can be loaded while the DACs are shut down
and, when SHDN goes high, the DACs will assume the new
output voltage. The AD8303 recovers from shutdown very
quickly. The voltage output settling time after shutdown is
typically only a few microseconds longer than the normal
settling time (Figure 20).
+3V TO +5V
SDI
CLK
CS
LDA
LDB
RS
MSB
SHDN
7
6
5
8
10
9
11
12
13
VDD
0.1µF 10µF
AD8303
VOUTA 2, 14
0V ≤ VOUT ≤ 2.0475V
VOUTA, VOUTB
VOUTB 14
2kΩ 500pF
AGND DGND
14
Figure 29. Unipolar Output Operation
UNIPOLAR OUTPUT OPERATION
This is the basic mode of operation for the AD8303. As shown
in Figure 29, the AD8303 has been designed to drive loads as
low as 2 kΩ in parallel with 500 pF. The code table for this
operation is shown in Table II.
Table II. Unipolar Code Table
Hexadecimal Number Decimal Number Analog Output
in DAC Register
in DAC Register Voltage (V)
FFF
4095
2.0475
801
2049
1.0245
800
2048
1.024
7FF
2047
1.0235
000 0 0
AD8303
GENERATING “BIPOLAR” OUTPUTS WITH A SINGLE
SUPPLY
To maximize output signal swings in single supply operation,
many circuit designs employ a “false-ground” configuration.
This method defines a voltage, usually at one half of full scale or
at one half of the power supply, as the “ground” reference.
Signals are then measured differentially from the false ground,
which produces a “quasi-bipolar” output swing.
The AD8303’s voltage reference output, combined with an op
amp, can provide a temperature compensated false-ground
reference, as shown in Figure 30. The op amp amplifies the
AD8303’s 1.0 V reference by 1.024 to provide an analog
common (false ground) at one-half scale (1.024 V). With this
method, the DAC output is ± 1.024 V (referenced to the false
ground). The “Quasi-Bipolar” code table is given in Table III.
+3V
13
VDD
2
VOUTA
AD8303
3
VREF
AGND DGND
14
+3V
OP193
100Ω
0.022µF
VOUT = ±1.024V
(REFERENCED TO
SIGNAL GROUND)
SIGNAL GROUND
(FALSE GROUND, +1.024V)
R2A
97.6kΩ
R1
2.4kΩ
R2B*
2kΩ
*ZERO-SCALE TRIM
1µF
Figure 30. A False-Ground Generator
Table III. Quasi-Bipolar Code Table
DAC Analog
Hexadecimal Decimal
Output Common
“Bipolar”
Number
Number In Voltage (False-Ground) Analog
in DAC Register DAC Register (V)
Voltage (V) Voltage (V)
FFF
4095
2.0475 1.024
+1.2035
801
2049
1.0245 1.024
0.0005
800
2048
1.024 1.024
0
7FF
2047
1.0235 1.024
–0.0005
000
0
0 1.024
–1.024
Since the AD8303’s reference voltage output limits are typical, a
trim potentiometer is included so that the “false-ground” output
can be adjusted to exactly 1.024 V. To maintain accuracy,
resistors R1 and R2A must be of the same type (preferably
metal film) to insure temperature coefficient matching. The
circuit includes compensation to allow for a 1 µF bypass
capacitor at the false-ground output. The benefit of a large
capacitor is that not only does the false ground present a very
low dc resistance to the load, but its ac impedance is low as
well.
REV. 0
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD8303.PDF ] | |
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