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PDF ADN8830 Data sheet ( Hoja de datos )
| Número de pieza | ADN8830 | |
| Descripción | Thermoelectric Cooler Controller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADN8830 (archivo pdf) en la parte inferior de esta página. Total 23 Páginas | ||
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FEATURES
High Efficiency
Small Size: 5 mm ؋ 5 mm LFCSP
Low Noise: <0.5% TEC Current Ripple
Long-Term Temperature Stability: ؎0.01؇C
Temperature Lock Indication
Temperature Monitoring Output
Oscillator Synchronization with an External Signal
Clock Phase Adjustment for Multiple Controllers
Programmable Switching Frequency up to 1 MHz
Thermistor Failure Alarm
Maximum TEC Voltage Programmability
APPLICATIONS
Thermoelectric Cooler (TEC) Temperature Control
Resistive Heating Element Control
Temperature Stabilization Substrate (TSS) Control
Thermoelectric Cooler Controller
ADN8830
GENERAL DESCRIPTION
The ADN8830 is a monolithic controller that drives a thermo-
electric cooler (TEC) to stabilize the temperature of a laser diode
or a passive component used in telecommunications equipment.
This device relies on a negative temperature coefficient (NTC)
thermistor to sense the temperature of the object attached to the
TEC. The target temperature is set with an analog input voltage
either from a DAC or an external resistor divider.
The loop is stabilized by a PID compensation amplifier with
high stability and low noise. The compensation network can be
adjusted by the user to optimize temperature settling time. The
component values for this network can be calculated based on
the thermal transfer function of the laser diode or obtained
from the lookup table given in the Application Notes section.
Voltage outputs are provided to monitor both the temperature of
the object and the voltage across the TEC. A voltage reference
of 2.5 V is also provided.
FROM
THERMISTOR
TEMPERATURE
SET
INPUT
VREF
FUNCTIONAL BLOCK DIAGRAM
PID COMPENSATION
NETWORK
TEMPERATURE
MEASUREMENT
AMPLIFIER
PWM
CONTROLLER
VOLTAGE
REFERENCE
OSCILLATOR
MOSFET
DRIVERS
P-CHANNEL
(UPPER MOSFET)
N-CHANNEL
P-CHANNEL
(LOWER MOSFET)
N-CHANNEL
FREQUENCY/PHASE
CONTROL
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/461-3113 © 2012 Analog Devices, Inc. All rights reserved.
1 page  
ADN8830
Pin No.
1
2
3
4
5
Mnemonic
THERMFAULT
THERMIN
SD
TEMPSET
TEMPLOCK
6 NC
7 VREF
8 AVDD
9 OUT B
10 N2
11 P2
12 TEMPCTL
13 COMPFB
14 COMPOUT
15 VLIM
16 VTEC
17 COMPSWOUT
18 COMPSWIN
19 OUT A
20 PVDD
21 P1
22 N1
23 PGND
24 COMPOSC
25 SYNCIN
26 FREQ
27 SOFTSTART
28 SYNCOUT
29 PHASE
30 AGND
31 TEMPOUT
32 NC
EP Exposed Pad
PIN FUNCTION DESCRIPTIONS
Type
Digital Output
Analog Input
Digital Input
Analog Input
Digital Output
Analog Output
Power
Analog Input
Analog Output
Analog Output
Analog Output
Analog Input
Analog Output
Analog Input
Analog Output
Analog Output
Analog Input
Analog Input
Power
Digital Output
Digital Output
Ground
Analog Input
Digital Input
Analog Input
Analog Input
Digital Output
Analog Input
Ground
Analog Output
Description
Indicates an Open or Short-Circuit Condition from Thermistor.
Thermistor Feedback Input.
Puts Device into Low Current Shutdown Mode. Active low.
Target Temperature Input.
Indicates when Thermistor Temperature is within ± 0.1°C of Target Tem-
perature as Set by TEMPSET Voltage.
No Connection, except as Noted in the Application Notes Section.
2.5 V Reference Voltage.
Power for Nondriver Sections. 3.0 V min; 5.5 V max.
Linear Output Feedback. Will typically connect to TEC+ pin of TEC.
Drives Linear Output External NMOS Gate.
Drives Linear Output External PMOS Gate.
Output of Error Amplifier. Connects to COMPFB through feedforward
section of compensation network.
Feedback Summing Node of Compensation Amplifier. Connects to
TEMPCTL and COMPOUT through compensation network.
Output of Compensation Amplifier. Connects to COMPFB through feed-
back section of compensation network.
Sets Maximum Voltage across TEC.
Indicates Relative Voltage across the TEC. The 1.5 V corresponds to 0 V
across TEC. The 3.0 V indicates maximum output voltage, maximum heat
transfer through TEC.
Compensation for Switching Amplifier.
Compensation for Switching Amplifier. Capacitor connected between
COMPSWIN and COMPSWOUT.
PWM Output Feedback. Will typically connect to TEC– pin of TEC.
Power for Output Driver Sections. 3.0 V min; 5.5 V max.
Drives PWM Output External PMOS Gate.
Drives PWM Output External NMOS Gate.
Power Ground. External NMOS devices connect to PGND. Can be
connected to digital ground as noise sensitivity at this node is not critical.
Connect as Indicated in the Application Notes Section.
Optional Clock Input. If not connected, clock frequency set by FREQ pin.
Sets Switching Frequency.
Controls Initialization Time for ADN8830 with Capacitor to Ground.
Phase Adjusted Clock Output. Phase set from PHASE pin. Can be used to
drive SYNCIN of other ADN8830 devices.
Sets Switching and SYNCOUT Clock Phase Relative to SYNCIN Clock.
Analog Ground. Should be low noise for highest accuracy.
Indication of Thermistor Temperature.
No Connection.
The exposed pad on the bottom of the package must be connected to VCC or the
GND plane.
–4– REV. D
5 Page 
ADN8830
To eliminate the resolution of the DAC as the principal source
of system error, the step size of each bit, VSTEP, should be lower
than the desired system resolution. A practical value for absolute
DAC resolution is the equivalent of 0.05°C. The value of VSTEP
should be less than the value of m from Equation 8 multiplied
by the desired temperature resolution, or
VSTEP < 0.05°C × m
(10)
where m is the slope of the voltage-to-temperature conversion
line, as found from Equation 8. From Design Example 2, where
m = 25 mV/°C, we see the DAC should have resolution better
than 1.25 mV per step.
The minimum number of bits required is then given as
( ) ( )Number of Bits = log VFS – log VSTEP
( )log 2
(11)
where VFS is the full-scale output voltage from the DAC, which
should be equal to the reference voltage from the ADN8830,
VREF = 2.47 V as given in the Specifications table for the
Reference Voltage. In this example, the minimum resolution is
11 bits. A 12-bit DAC, such as the AD7390, can be readily
found.
It is important that the full-scale voltage input to the DAC is tied
to the ADN8830 reference voltage, as shown in Figure 4. This
eliminates errors from slight variances of VREF.
Thermistor Fault and Temperature Lock Indications
Both the THERMFAULT (Pin 1) and TEMPLOCK (Pin 5)
outputs are CMOS compatible outputs that are active high.
THERMFAULT will be a logic low while the thermistor is
operating normally and will go to a logic high if a short or
open is detected at THERMIN (Pin 2). The trip voltage for
THERMFAULT is when THERMIN falls below 0.2 V or
exceeds 2.0 V. THERMFAULT provides only an indication of
a fault condition and does not activate any shutdown or protec-
tion circuitry on the ADN8830. To shut down the ADN8830, a
logic low voltage must be asserted on Pin 3, as described in the
Shutdown Mode section.
TEMPLOCK will output a logic high when the voltage at
THERMIN is within 2.5 mV of TEMPSET. This voltage can
be related to temperature by solving for m from Equation 8. For
most laser diode applications, 2.5 mV is equivalent to ± 0.1°C.
If the voltage difference between THERMIN and TEMPSET is
greater than 2.5 mV, then TEMPLOCK will output a logic low.
The input offset voltage of the ADN8830 is guaranteed to within
250 μV, which for most applications is within ± 0.01°C.
Setting the Switching Frequency
The ADN8830 has an internal oscillator to generate the switch-
ing frequency for the output stage. This oscillator can be either
set in free-run mode or synchronized to an external clock
signal. For free-run operation, SYNCIN (Pin 25) should be
connected to ground and COMPOSC (Pin 24) should be
connected to AVDD. The switching frequency is then set by a
single resistor connected from FREQ (Pin 26) to ground.
Table I shows RFREQ for some common switching frequencies.
Table I. Switching Frequencies vs. RFREQ
fSWITCH
100 kHz
250 kHz
500 kHz
750 kHz
1 MHz
RFREQ
1.5 MΩ
600 kΩ
300 kΩ
200 kΩ
150 kΩ
For other frequencies, the value for this resistor, RFREQ, should
be set to
RFREQ
=
150 × 109
fSWITCH
(12)
where fSWITCH is the switching frequency in Hz.
Higher switching frequencies reduce the voltage ripple across
the TEC. However, high switch frequencies will create more
power dissipation in the external transistors. This is due to the
more frequent charging and discharging of the transistors’ gate
capacitances. If large transistors are needed for a high output
current application, faster switching frequencies could reduce
the overall power efficiency of the circuit. This is covered in
detail in the Calculating Power Dissipation and Efficiency section.
The switching frequency of the ADN8830 can be synchronized
with an external clock by connecting the clock signal to SYNCIN
(Pin 25). Pin 24 should also be connected to an R-C network, as
shown in Figure 6. This network is simply used to compensate a
PLL to lock on to the external clock. To ensure the quickest
synchronization lock-in time, RFREQ should be set to 1.5 MΩ.
ADN8830
COMPOSC
24
1nF
1k⍀ 0.1F
FREQ
26 1.5M⍀
Figure 6. Using an R-C Network on Pin 24 with
an External Clock
The relative phase of the ADN8830 internal oscillator compared
to the external clock signal can be adjusted. This is accomplished
by adjusting the voltage to PHASE (Pin 29) according to TPCs 3
and 4. The phase shift versus voltage can be approximated as
Phase Shift° = 360° × VPHASE
VREF
(13)
where VPHASE is the voltage at Pin 29, and VREF has a typical
value of 2.47 V.
To ensure the oscillator operates correctly, VPHASE should remain
higher than 100 mV and lower than 2.3 V. This is required for
either internal clock or external synchronization operation. A
resistor divider from VREF to ground can establish this voltage
easily, although any voltage source, such as a DAC, could be used
as well. If phase is not a consideration, for example with a single
ADN8830 being used, Pin 29 can be tied to Pin 6, which pro-
vides a 1.5 V reference voltage.
–10–
REV. D
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet ADN8830.PDF ] | |
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