ADM3485E Datasheet PDF - Analog Devices
Part Number | ADM3485E | |
Description | EIA RS-485/RS-422 Transceiver | |
Manufacturers | Analog Devices | |
Logo | ||
There is a preview and ADM3485E download ( pdf file ) link at the bottom of this page. Total 17 Pages |
Preview 1 page No Preview Available ! ±15 kV ESD-Protected, 3.3 V,12 Mbps,
EIA RS-485/RS-422 Transceiver
ADM3485E
FEATURES
TIA/EIA RS-485/RS-422 compliant
±15 kV ESD protection on RS-485 input/output pins
12 Mbps data rate
Half-duplex transceiver
Up to 32 nodes on the bus
Receiver open-circuit, fail-safe design
Low power shutdown current
Outputs high-Z when disabled or powered off
Common-mode input range: −7 V to +12 V
Thermal shutdown and short-circuit protection
Industry-standard 75176 pinout
8-lead narrow SOIC package
APPLICATIONS
Power/energy metering
Telecommunications
EMI-sensitive systems
Industrial control
Local area networks
GENERAL DESCRIPTION
The ADM3485E is a 3.3 V, low power data transceiver with
±15 kV ESD protection, suitable for half-duplex communi-
cation on multipoint bus transmission lines. The ADM3485E
is designed for balanced data transmission and complies with
TIA/EIA standards RS485 and RS-422. The ADM3485E is a
half-duplex transceiver that shares differential lines and has
separate enable inputs for the driver and the receiver.
The devices have a 12 kΩ receiver input impedance, which
allows up to 32 transceivers on a bus. Because only one driver
FUNCTIONAL BLOCK DIAGRAM
ADM3485E
RO R
RE
DE
DI D
B
A
Figure 1.
should be enabled at any time, the output of a disabled or
powered-down driver is tristated to avoid overloading the bus.
The receiver has a fail-safe feature that ensures a logic high
output when the inputs are floating. Excessive power dissipation
caused by bus contention or by output shorting is prevented
with a thermal shutdown circuit.
The part is fully specified over the industrial temperature range
and is available in an 8-lead narrow SOIC package.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2000-2010 Analog Devices, Inc. All rights reserved.
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ADM3485E
TIMING SPECIFICATIONS
VCC = 3.3 V, TA = 25°C.
Table 2.
Parameter
DRIVER
Maximum Data Rate
Differential Output Delay
Differential Output Transition Time
Propagation Delay
From Low to High Level
From High to Low Level
|tPLH − tPHL| Propagation Delay Skew
Enable/Disable Timing
Enable Time to Low Level
Enable Time to High Level
Disable Time from Low Level
Disable Time from High Level
Enable Time from Shutdown to Low Level
Enable Time from Shutdown to High Level
RECEIVER
Propagation Delay
From Low to High Level
From High to Low Level
|tRPLH − tRPHL| Propagation Delay Skew
Enable/Disable Timing
Enable Time to Low Level
Enable Time to High Level
Disable Time from Low Level
Disable Time from High Level
Enable Time from Shutdown to Low Level
Enable Time from Shutdown to High Level
Time to Shutdown1
Symbol Min Typ Max Unit Test Conditions/Comments
12 15
tDD 1 22 35 ns RL = 60 Ω, CL1 = CL2 = 15 pF (see Figure 6)
tTD 3 11 25 ns RL = 60 Ω, CL1 = CL2 = 15 pF (see Figure 6)
tPLH 7 23 35 ns RL = 27 Ω (see Figure 7)
tPHL 7 23 35 ns RL = 27 Ω (see Figure 7)
tPDS –1.4 ±8 ns RL = 27 Ω (see Figure 7)
tPZL 42 90 ns RL = 110 Ω (see Figure 9)
tPZH 42 90 ns RL = 110 Ω (see Figure 8)
tPLZ 35 80 ns RL = 110 Ω (see Figure 9)
tPHZ 35 80 ns RL = 110 Ω (see Figure 8)
tPSL 650 900 ns RL = 110 Ω (see Figure 9)
tPSH 650 900 ns RL = 110 Ω (see Figure 8)
tRPLH 25 62 90 ns VID = 0 V to 3.0 V, CL = 15 pF (see Figure 10)
tRPHL 25 62 90 ns VID = 0 V to 3.0 V, CL = 15 pF (see Figure 10)
tRPDS 6 ±10 ns VID = 0 V to 3.0 V, CL = 15 pF (see Figure 10)
tRPZL 25 50 ns CL = 15 pF (see Figure 11)
tRPZH 25 50 ns CL = 15 pF (see Figure 11)
tRPLZ 25 45 ns CL = 15 pF (see Figure 11)
tRPHZ 25 45 ns CL = 15 pF (see Figure 11)
tRPSL 720 1400 ns CL = 15 pF (see Figure 11)
tRPSH 720 1400 ns CL = 15 pF (see Figure 11)
tSHDN
80 190 300 ns
1 The transceivers are put into shutdown mode by bringing the RE high and the DE low. If the inputs are in this state for less than 80 ns, the parts are guaranteed not to
enter shutdown. If the parts are in this state for 300 ns or more, the parts are guaranteed to enter shutdown.
Rev. D | Page 4 of 16
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