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PDF AK4527B Data sheet ( Hoja de datos )
| Número de pieza | AK4527B | |
| Descripción | High Performance Multi-channel Audio CODEC | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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ASAHI KASEI
[AK4527B]
AK4527B
High Performance Multi-channel Audio CODEC
GENERAL DESCRIPTION
The AK4527B is a single chip CODEC that includes two channels of ADC and six channels of DAC. The
ADC outputs 24bit data and the DAC accepts up to 24bit input data. The ADC has the Enhanced Dual Bit
architecture with wide dynamic range. The DAC introduces the new developed Advanced Multi-Bit
architecture, and achieves wider dynamic range and lower outband noise. An auxiliary digital audio input
interface maybe used instead of the ADC for passing audio data to the primary audio output port. Control
may be set directly by pins or programmed through a separate serial interface.
The AK4527B has a dynamic range of 102dB for ADC, 106dB for DAC and is well suited for digital
surround for home theater and car audio. An AC-3 system can be built with a IEC60958(SPDIF) receiver
such as the AK4112A. The AK4527B is available in a small 44pin LQFP package which will reduce
system space.
*AC-3 is a trademark of Dolby Laboratories.
FEATURES
o 2ch 24bit ADC
- 64x Oversampling
- Sampling Rate up to 96kHz
- Linear Phase Digital Anti-Alias Filter
- Differential Inputs with single-ended use capability
- S/(N+D): 92dB
- Dynamic Range, S/N: 102dB
- Digital HPF for offset cancellation
- I/F format: MSB justified or I2S
- Overflow flag
o 6ch 24bit DAC
- 128x Oversampling
- Sampling Rate up to 96kHz
- 24bit 8 times Digital Filter
- Single-Ended Outputs
- On-chip Switched-Capacitor Filter
- S/(N+D): 90dB
- Dynamic Range, S/N: 106dB
- I/F format: MSB justified, LSB justified(20bit,24bit) or I2S
- Individual channel digital volume with 256 levels and 0.5dB step
- Soft mute
- De-emphasis for 32kHz, 44.1kHz and 48kHz
- Zero Detect Function
o High Jitter Tolerance
o TTL Level Digital I/F
o 3-wire Serial and I2C Bus µP I/F for mode setting
o Master clock:256fs, 384fs or 512fs for fs=32kHz to 48kHz
128fs, 192fs or 256fs for fs=64kHz to 96kHz
o Power Supply: 4.5 to 5.5V
o Power Supply for output buffer: 2.7 to 5.5V
o Small 44pin LQFP
MS0056-E-00
-1-
2000/10
1 page  
ASAHI KASEI
No. Pin Name
1 SDOS
2 I2C
3 SMUTE
4 BICK
5 LRCK
6 SDTI1
7 SDTI2
8 SDTI3
9 SDTO
10 DAUX
11 DFS
12 NC
13 DZFE
14 TVDD
15 DVDD
16 DVSS
17 PDN
18 TST
19 NC
20 ADIF
21 CAD1
22 CAD0
[AK4527B]
PIN/FUNCTION
I/O Function
I SDTO Source Select Pin
(Note 1)
“L”: Internal ADC output, “H”: DAUX input
I Control Mode Select Pin
“L”: 3-wire Serial, “H”: I2C Bus
I Soft Mute Pin
(Note 1)
When this pin goes to “H”, soft mute cycle is initialized.
When returning to “L”, the output mute releases.
I Audio Serial Data Clock Pin
I Input Channel Clock Pin
I DAC1 Audio Serial Data Input Pin
I DAC2 Audio Serial Data Input Pin
I DAC3 Audio Serial Data Input Pin
O Audio Serial Data Output Pin
I AUX Audio Serial Data Input Pin
I Double Speed Sampling Mode Pin (Note 1)
“L”: Normal Speed, “H”: Double Speed
- No Connect
No internal bonding.
I Zero Input Detect Enable Pin
“L”: mode 7 (disable) at parallel mode,
zero detect mode is selectable by DZFM2-0 bits at serial mode
“H”: mode 0 (DZF1 is AND of all six channels)
- Output Buffer Power Supply Pin, 2.7V∼5.5V
- Digital Power Supply Pin, 4.5V∼5.5V
- Digital Ground Pin, 0V
I Power-Down & Reset Pin
When “L”, the AK4527B is powered-down and the control registers are reset to default
state. If the state of P/S or CAD0-1 changes, then the AK4527B must be reset by PDN.
I Test Pin
This pin should be connected to DVSS.
- No Connect
No internal bonding.
I Analog Input Format Select Pin
“H”: Full-differential input, “L”: Single-ended input
I Chip Address 1 Pin
I Chip Address 0 Pin
MS0056-E-00
-5-
2000/10
5 Page 
ASAHI KASEI
[AK4527B]
Parameter
Control Interface Timing (3-wire Serial mode):
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Rise Time of CSN
Fall Time of CSN
Rise Time of CCLK
Fall Time of CCLK
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 20)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Power-down & Reset Timing
PDN Pulse Width
PDN “↑” to SDTO valid
(Note 21)
(Note 22)
Symbol
min typ
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tR1
tF1
tR2
tF2
200
80
80
40
40
0.025*1/fs
50
50
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
-
4.7
4.0
4.7
4.0
4.7
0
0.25
-
-
4.0
0
tPD
tPDV
150
522
Notes: 20. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
21. The AK4527B can be reset by bringing PDN “L” to “H” upon power-up.
22. These cycles are the number of LRCK rising from PDN rising.
23. I2C is a registered trademark of Philips Semiconductors.
max Units
ns
ns
ns
ns
ns
ns
ns
ns
20 ns
20 ns
20 ns
20 ns
100 kHz
- µs
- µs
- µs
- µs
- µs
- µs
- µs
1.0 µs
0.3 µs
- µs
50 ns
ns
1/fs
Purchase of Asahi Kasei Microsystems Co., Ltd I2C components conveys a license under the Philips
I2C patent to use the components in the I2C system, provided the system conform to the I2C
specifications defined by Philips.
MS0056-E-00
- 11 -
2000/10
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AK4527B.PDF ] | |
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