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PDF M28F101 Data sheet ( Hoja de datos )
| Número de pieza | M28F101 | |
| Descripción | 1 Mb FLASH MEMORY | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M28F101
1 Mb (128K x 8, Chip Erase) FLASH MEMORY
5V ±10% SUPPLY VOLTAGE
12V PROGRAMMING VOLTAGE
FAST ACCESS TIME: 70ns
BYTE PROGRAMING TIME: 10µs typical
ELECTRICAL CHIP ERASE in 1s RANGE
LOW POWER CONSUMPTION
– Stand-by Current: 100µA max
10,000 ERASE/PROGRAM CYCLES
INTEGRATED ERASE/PROGRAM-STOP
TIMER
OTP COMPATIBLE PACKAGES and PINOUTS
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 07h
DESCRIPTION
The M28F101 FLASH Memory is a non-volatile
memory which may be erased electrically at the
chip level and programmed byte-by-byte. It is or-
ganised as 128K bytes of 8 bits. It uses a command
register architecture to select the operating modes
and thus provides a simple microprocessor inter-
face. The M28F101 FLASH Memory is suitable for
applications where the memory has to be repro-
grammed in the equipment. The access time of
70ns makes the device suitable for use in high
speed microprocessor systems.
32
1
PDIP32 (P)
PLCC32 (K)
TSOP32 (N)
8 x 20 mm
Figure 1. Logic Diagram
VCC VPP
17
A0-A16
8
DQ0-DQ7
Table 1. Signal Names
A0-A16
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E Chip Enable
G Output Enable
W Write Enable
VPP Program Supply
VCC Supply Voltage
VSS Ground
W M28F101
E
G
VSS
AI00666B
April 1997
1/23
1 page  
Table 6. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
SRAM Interface Levels
≤ 10ns
0 to 3V
1.5V
M28F101
EPROM Interface Levels
≤ 10ns
0.45V to 2.4V
0.8V and 2V
Figure 3. AC Testing Input Output Waveform
SRAM Interface
3V
0V
EPROM Interface
2.4V
0.45V
1.5V
2.0V
0.8V
AI01275
Figure 4. AC Testing Load Circuit
1.3V
1N914
DEVICE
UNDER
TEST
3.3kΩ
OUT
CL = 30pF or 100pF
CL = 30pF for SRAM Interface
CL = 100pF for EPROM Interface
CL includes JIG capacitance
AI01276
Table 7. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
Parameter
Test Condition
CIN Input Capacitance
VIN = 0V
COUT
Output Capacitance
Note: 1. Sampled only, not 100% test.ed
VOUT = 0V
Min Max Unit
6 pF
12 pF
READ/WRITE MODES (cont’d)
A write to the command register is made by bringing
W Low while E is Low. The falling edge of W latches
Addresses, while the rising edge latches Data,
which are used for those commands that require
address inputs, command input or provide data
output.
The supply voltage VCC and the program voltage
VPP can be applied in any order. When the device
is powered up or when VPP is ≤ 6.5V the contents
of the command register defaults to 00h, thus
automatically setting-up Read operations. In addi-
tion a specific command may be used to set the
command register to 00h for reading the memory.
The system designer may chose to provide a con-
stant high VPP and use the register commands for
all operations, or to switch the VPP from low to high
only when needing to erase or program the mem-
ory. All command register access is inhibited when
VCC falls below the Erase/Write Lockout Voltage
(VLKO) of 2.5V.
If the device is deselected during Erasure, Pro-
gramming or Verification it will draw active supply
currents until the operations are terminated.
The device is protected against stress caused by
long erase or program times. If the end of Erase or
Programming operations are not terminated by a
Verify cycle within a maximum time permitted, an
internal stop timer automatically stops the opera-
tion. The device remains in an inactive state, ready
to start a Verify or Reset Mode operation.
5/23
5 Page 
M28F101
Table 10A. Read/Write Mode AC Characteristics, W and E Controlled
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
Symbol Alt
Parameter
tVPHEL
VPP High to Chip Enable Low
tVPHWL
VPP High to Write Enable Low
tWHWH3 tWC Write Cycle Time
tAVWL
tAS Address Valid to Write Enable Low
tAVEL
Address Valid to Chip Enable Low
tWLAX
tAH Write Enable Low to Address Transition
tELAX
Chip Enable Low to Address Transition
tELWL
tCS Chip Enable Low to Write Enable Low
tWLEL
Write Enable Low to Chip Enable Low
tGHWL
Output Enable High to Write Enable
Low
tGHEL
Output Enable High to Chip Enable Low
tDVWH
tDS Input Valid to Write Enable High
tDVEH
Input Valid to Chip Enable High
tWLWH
tWP
Write Enable Low to Write Enable High
(Write Pulse)
tELEH
Chip Enable Low to Chip Enable High
(Write Pulse)
tWHDX tDH Write Enable High to Input Transition
tEHDX
Chip Enable High to Input Transition
tWHWH1
Duration of Program Operation
tEHEH1
Duration of Program Operation
tWHWH2
Duration of Erase Operation
tWHEH tCH Write Enable High to Chip Enable High
tEHWH
Chip Enable High to Write Enable High
tWHWL tWPH Write Enable High to Write Enable Low
tEHEL
Chip Enable High to Chip Enable Low
tWHGL
Write Enable High to Output Enable
Low
tEHGL
Chip Enable High to Output Enable Low
tAVQV
tELQX (1)
tACC Addess Valid to data Output
tLZ Chip Enable Low to Output Transition
tELQV
tGLQX (1)
tCE Chip Enable Low to Output Valid
tOLZ Output Enable Low to Output Transition
tGLQV
tEHQZ (1)
tGHQZ (1)
tOE Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
tDF Output Enable High to Output Hi-Z
tAXQX
tOH Address Transition to Output Transition
Note: 1. Sampled only, not 100% tested.
-70
VCC=5V±5%
SRAM
Interface
Min Max
1
1
70
0
0
40
50
10
0
0
0
30
30
35
35
10
10
9.5
9.5
9.5
0
0
20
20
6
6
70
0
70
0
40
30
30
0
M28F101
-90
VCC=5V±10%
EPROM
Interface
Min Max
1
1
90
0
0
40
60
15
0
0
0
40
35
40
45
10
10
9.5
9.5
9.5
0
0
20
20
6
6
90
0
90
0
40
40
30
0
-100
VCC=5V±10%
EPROM
Interface
Min Max
1
1
100
0
0
40
60
15
0
0
0
40
40
40
45
10
10
9.5
9.5
9.5
0
0
20
20
6
6
100
0
100
0
45
40
30
0
Unit
µs
µs
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
µs
µs
ms
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
11/23
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet M28F101.PDF ] | |
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