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PDF Am29LV160M Data sheet ( Hoja de datos )
| Número de pieza | Am29LV160M | |
| Descripción | 16 Megabit 3.0 Volt-only Boot Sector Flash Memory | |
| Fabricantes | AMD | |
| Logotipo |  |
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ADVANCE INFORMATION
Am29LV160M
16 Megabit (2 M x 8-Bit/1 M x 16-Bit) MirrorBitTM
3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
s Manufactured on 0.23 µm MirrorBitTM process
technology
— Fully compatible with Am29LV160D device
s High performance
— Access times as fast as 70 ns
s Ultra low power consumption (typical values at
5 MHz)
— 400 nA Automatic Sleep mode current
— 400 nA standby mode current
— 15 mA read current
— 40 mA program/erase current
s Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
thirty-one 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
thirty-one 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to prevent
any program or erase operations within that sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
s Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
s Top or bottom boot block configurations
available
s Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
s Minimum 1,000,000 write cycle guarantee
per sector
s 20-year data retention at 125°C
— Reliable operation for the life of the system
s Package option
— 48-ball FBGA
— 48-pin TSOP
— 44-pin SO
— 64-ball Fortified BGA
s CFI (Common Flash Interface) compliant
— Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
s Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
s Data# Polling and toggle bits
— Provides a software method of detecting program
or erase operation completion
s Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion (not available
on 44-pin SO)
s Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
s Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 25974 Rev: A Amendment/1
Issue Date: July 3, 2002
1 page  
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard TSOP
Reverse TSOP
48 A16
47 BYTE#
46 VSS
45 DQ15/A-1
44 DQ7
43 DQ14
42 DQ6
41 DQ13
40 DQ5
39 DQ12
38 DQ4
37 VCC
36 DQ11
35 DQ3
34 DQ10
33 DQ2
32 DQ9
31 DQ1
30 DQ8
29 DQ0
28 OE#
27 VSS
26 CE#
25 A0
48 A15
47 A14
46 A13
45 A12
44 A11
43 A10
42 A9
41 A8
40 A19
39 NC
38 WE#
37 RESET#
36 NC
35 NC
34 RY/BY#
33 A18
32 A17
31 A7
30 A6
29 A5
28 A4
27 A3
26 A2
25 A1
Am29LV160M
5
5 Page 
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more
information.
The device features an Unlock Bypass mode to facil-
itate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a word or byte, instead of four. The
“Word/Byte Program Command Sequence” section
has details on programming data to the device using
both standard and Unlock Bypass command
sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector
address” consists of the address bits required to
uniquely select a sector. The “Command Definitions”
section has details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings
apply in this mode. Refer to the “Autoselect Mode” and
“Autoselect Command Sequence” sections for more
information.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VCC ± 0.3 V, the device will be in the standby mode, but
the standby current will be greater. The device requires
standard access time (tCE) for read access when the
device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
In the DC Characteristics table, ICC3 and ICC4 repre-
sents the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically
enables this mode when addresses remain stable for
tACC + 30 ns. The automatic sleep mode is
independent of the CE#, WE#, and OE# control
signals. Standard address access timings provide new
data when addresses are changed. While in sleep
mode, output data is latched and always available to
the system. ICC4 in the DC Characteristics table
represents the automatic sleep mode current
specification.
Am29LV160M
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet Am29LV160M.PDF ] | |
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