PDF AM29F040B Data sheet ( Hoja de datos )

Número de pieza	AM29F040B
Descripción	4 Megabit CMOS 5.0 Volt-only Uniform Sector Flash Memory
Fabricantes	AMD
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Am29F040B 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory DISTINCTIVE CHARACTERISTICS s 5.0 V ± 10% for read and write operations — Minimizes system level power requirements s Manufactured on 0.32 µm process technology — Compatible with 0.5 µm Am29F040 device s High performance — Access times as fast as 55 ns s Low power consumption — 20 mA typical active read current — 30 mA typical program/erase current — 1 µA typical standby current (standard access time to active mode) s Flexible sector architecture — 8 uniform sectors of 64 Kbytes each — Any combination of sectors can be erased — Supports full chip erase — Sector protection: A hardware method of locking sectors to prevent any program or erase operations within that sector s Embedded Algorithms — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors — Embedded Program algorithm automatically writes and verifies bytes at specified addresses s Minimum 1,000,000 program/erase cycles per sector guaranteed s 20-year data retention at 125°C — Reliable operation for the life of the system s Package options — 32-pin PLCC, TSOP, or PDIP s Compatible with JEDEC standards — Pinout and software compatible with single-power-supply Flash standard — Superior inadvertent write protection s Data# Polling and toggle bits — Provides a software method of detecting program or erase cycle completion s Erase Suspend/Erase Resume — Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 21445 Rev: E Amendment/0 Issue Date: November 29, 2000 1 page CONNECTION DIAGRAMS A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 PDIP 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 VCC WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 4 3 2 1 32 31 30 5 29 6 28 7 27 8 26 9 PLCC 10 25 24 11 23 12 22 13 21 14 15 16 17 18 19 20 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 A11 A9 A8 A13 A14 A17 WE# VCC A18 A16 A15 A12 A7 A6 A5 A4 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-Pin Standard TSOP 32-Pin Reverse TSOP 32 OE# 31 A10 30 CE# 29 DQ7 28 DQ6 27 DQ5 26 DQ4 25 DQ3 24 VSS 23 DQ2 22 DQ1 21 DQ0 20 A0 19 A1 18 A2 17 A3 32 A11 31 A9 30 A8 29 A13 28 A14 27 A17 26 WE# 25 VCC 24 A18 23 A16 22 A15 21 A12 20 A7 19 A6 18 A5 17 A4 Am29F040B 5 5 Page COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the im- proper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Em- bedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The sys- tem can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more infor- mation on this mode. The system must issue the reset command to re-en- able the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Com- mand” section, next. See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parame- ters, and Read Operation Timings diagram shows the timing diagram. Reset Command Writing the reset command to the device resets the de- vice to reading array data. Address bits are don’t care for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ig- nores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to read- ing array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This method is an alternative to that shown in the Autoselect Codes (High Voltage Method) table, which is intended for PROM program- mers and requires VID on address bit A9. The autoselect command sequence is initiated by writ- ing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h or retrieves the manu- facturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector ad- dress (SA) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. Refer to the Sector Address tables for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Byte Program Command Sequence Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verify the pro- grammed cell margin. The Command Definitions take shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and ad- dresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. See “Write Operation Status” for informa- tion on these status bits. Am29F040B 11 11 Page

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