PDF MCP19122 Data sheet ( Hoja de datos )

Número de pieza	MCP19122
Descripción	Digitally Enhanced Power Analog Controller
Fabricantes	Microchip
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MCP19122/3 Digitally Enhanced Power Analog Controller with Integrated Synchronous Driver Synchronous Buck Features • Input Voltage: 4.5V to 40V (operating), 48V (non-operating) • Output Voltage: 0.3V to 16V - 0.1% typical output voltage accuracy - Greater than 16V requires external divider • Switching Frequency: 100 kHz to 1.6 MHz • Shutdown Quiescent Current: 50 µA Typical • High-Drive: - +5V Gate Drive - 2A Source Current - 2A Sink Current • Low-Drive: - +5V Gate Drive - 2A Source Current - 4A Sink Current • Emulated Average Current Mode Control • Differential Remote Output Sense • Multi-Phase Systems: - Master or Slave - Frequency Synchronized - Common Current Sense Signal • Multiple Output Systems: - Master or Slave - Frequency Synchronized • AEC-Q100 Qualified • Configureable Parameters: - Overcurrent Limit - Input Undervoltage Lockout - Input Overvoltage - Output Overvoltage - Output Undervoltage - Internal Analog Compensation - Soft Start Profile - Synchronous Driver Dead Time - Switching Frequency • Thermal Shutdown Microcontroller Features • Precision 8 MHz Internal Oscillator Block: - Factory Calibrated • Interrupt Capable - Firmware - Interrupt-on-Change Pins • Only 35 Instructions to Learn • 4096 Words On-Chip Program Memory • High Endurance Flash: - 100,000 Write Flash Endurance - Flash Retention: >40 years • Watchdog Timer (WDT) with Independent Oscillator for Reliable Operation • Programmable Code Protection • In-Circuit Debug (ICD) via Two Pins (MCP19123) • In-Circuit Serial Programming™ (ICSP™) via Two Pins • 12 I/O Pins and One Input-Only Pin (MCP19122) - 3 Open Drain Pins - 2 Weak Current Source Pins • 16 I/O Pins and One Input-Only Pin (MCP19123) - 3 Open Drain Pins - 2 Weak Current Source Pins • Analog-to-Digital Converter (ADC): - 10-bit Resolution - 24 Internal Channels - 8 External Channels • Timer0: 8-bit Timer/Counter with 8-Bit Prescaler • Enhanced Timer1: - 16-bit Timer/Counter with Prescaler - 2 Selectable Clock Sources - External Gate Input Mode • Timer2: 8-Bit Timer/Counter with Prescaler - 8-bit Period Register • Capture, Compare Module • I2CTM Communication: - 7-bit Address Masking - 2 Dedicated Address Registers - SMBus/PMBusTM Compatibility  2017 Microchip Technology Inc. DS20005750A-page 1 1 page MCP19122/3 TABLE 2: 28-PIN QFN (MCP19123) SUMMARY I/O Basic Additional GPA0 GPA1 1 2 Y Y AN0 — AN1 — — IOC — IOC Y Y — Analog Debug Output (1) — Sync Signal In/Out (2, 3) GPA2 3 Y AN2 T0CKI — IOC Y — Weak Current Source INT GPA3 5 Y AN3 — — IOC Y — Weak Current Source Timer1 Gate Input 1 GPA4 9 N — — — IOC N — — GPA5 8 N — — — IOC(4) Y(5) MCLR — GPA6 7 N — — — IOC N — CCD Input 1 GPA7 6 N — — SCL IOC N — — GPB0 24 N — — SDA IOC N — — GPB1 26 Y AN4 — — IOC Y — Current Sense Output Current Reference Input(3) GPB2 GPB3 28 23 Y N AN5 — —— — IOC — IOC Y Y — Timer1 Gate Input 2 — Clock Signal In/Out (2, 3) GPB4 4 Y AN6 — — IOC Y ICSPDAT ICDDAT — GPB5 27 Y AN7 — — IOC Y ICSPCLK ICDCLK — GPB6 10 N — — — IOC Y — CCD Input 2 GPB7 25 N — — — IOC Y — External A/D Reference VIN 21 N — — — — — VIN Device Input Voltage VDD 22 N — — — — — VDD Internal Regulator Output GND 11 N ——— — — GND Small Signal Ground PGND 16 N ——— — — LDRV 17 N ——— — — — — Large Signal Ground Low-Side MOSFET Connection HDRV 19 N ——— — — — High-Side MOSFET Connection PHASE 18 N ——— — — — Switch Node BOOT 20 N ——— — — — Floating Bootstrap Supply +VSEN 13 N ——— — — –VSEN 12 N ——— — — — — Output Voltage Differential Sense Output Voltage Differential Sense ISP 15 N — — — — — — Current Sense Input ISN 14 N — — — — — — Current Sense Input EP — — — — — — — — Exposed Pad Note 1: 2: 3: 4: 5: The Analog Debug Output is selected when the BUFFCON<BNCHEN> bit is set. Selected when device is functioning as multiple output master or slave by proper configuration of the MSC<2:0> bits in the MODECON register. Selected when device is functioning as multi-phase master or slave by proper configuration of the MSC<2:0> bits in the MODECON register. The IOC is disabled when MCLR is enabled. Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.  2017 Microchip Technology Inc. DS20005750A-page 5 5 Page MCP19122/3 FIGURE 1-3: MICROCONTROLLER CORE BLOCK DIAGRAM Configuration Flash 4K x 14 Program Memory Program Bus 14 Instruction reg 13 Program Counter Data Bus 8 8 Level Stack (13-bit) RAM 256 bytes RegFiisleters RAM Addr 9 Addr MUX Direct Addr 7 Indirect 8 Addr FSR reg STATUS reg 8 Instruction Decode & Control CLKIN CLKOUT Timing Generation 8 MHz Internal Oscillator T1G T2G T0CKI Timer0 Power-up Timer Power-on Reset Watchdog Timer Brown-out Reset 3 MUX ALU 8 W reg MCLR VIN VSS Timer1 OUV COMP Timer2 PORTA PORTB GPA0 GPA1 GPA2 GPA3 GPA4 GPA5 GPA6 GPA7 GPB0 GPB1 GPB2 GPB3 GPB4(1) GPB5(1) GPB6(1) GPB7(1) MSSP SDA SCL PMDATL Self read/ write flash memory EEADDR Analog interface registers CCD CCD1 CCD2 Note 1: Not implemented on the MCP19122. PWM  2017 Microchip Technology Inc. DS20005750A-page 11 11 Page

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