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PDF LTC2320-16 Data sheet ( Hoja de datos )
| Número de pieza | LTC2320-16 | |
| Descripción | 1.5Msps/Ch Simultaneous Sampling ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC2320-16 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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FEATURES
nn 1.5Msps/Ch Throughput Rate
nn Eight Simultaneously Sampling Channels
nn Guaranteed 16-Bit, No Missing Codes
nn 8VP-P Differential Inputs with Wide Input
Common Mode Range
nn 82dB SNR (Typ) at fIN = 500kHz
nn –90dB THD (Typ) at fIN = 500kHz
nn Guaranteed Operation to 125°C
nn Single 3.3V or 5V Supply
nn Low Drift (20ppm/°C Max) 2.048V or 4.096V
Internal Reference
nn 1.8V to 2.5V I/O Voltages
nn CMOS or LVDS SPI-Compatible Serial I/O
nn Power Dissipation 20mW/Ch (Typ)
nn Small 52-Pin (7mm × 8mm) QFN Package
APPLICATIONS
nn High Speed Data Acquisition Systems
nn Communications
nn Optical Networking
nn Multiphase Motor Control
LTC2320-16
Octal, 16-Bit, 1.5Msps/Ch
Simultaneous Sampling ADC
DESCRIPTION
The LTC®2320-16 is a low noise, high speed octal 16‑bit
successive approximation register (SAR) ADC with
differential inputs and wide input common mode range.
Operating from a single 3.3V or 5V supply, the LTC2320-16
has an 8VP-P differential input range, making it ideal for
applications which require a wide dynamic range with high
common mode rejection. The LTC2320-16 achieves ±2LSB
INL typical, no missing codes at 16 bits and 82dB SNR.
The LTC2320-16 has an onboard low drift (20ppm/°C max)
2.048V or 4.096V temperature-compensated reference.
The LTC2320-16 also has a high speed SPI-compatible
serial interface that supports CMOS or LVDS. The fast
1.5Msps per channel throughput with no latency makes
the LTC2320-16 ideally suited for a wide variety of high
speed applications. The LTC2320-16 dissipates only 20mW
per channel and offers nap and sleep modes to reduce the
power consumption to 26μW for further power savings
during inactive periods.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
TYPICAL APPLICATION
3.3V OR 5V
10µF
1µF
1.8V TO 2.5V
TRUE DIFFERENTIAL INPUTS
NO CONFIGURATION REQUIRED
IN+, IN–
ARBITRARY
VDD
DIFFERENTIAL
VDD
0V 0V
BIPOLAR
VDD
UNIPOLAR
VDD
0V 0V
EIGHT SIMULTANEOUS
SAMPLING CHANNELS
AAIINN11+– S/H
AAIINN22+– S/H
MUX
VDD GND
16-BIT
SAR ADC
GND OVDD
CMOS/LVDS
SDR/DDR
REFBUFEN
AAIINN33+– S/H
AAIINN44+– S/H
AAIINN55+– S/H
AAIINN66+– S/H
MUX
16-BIT
SAR ADC
LTC2320-16
MUX
16-BIT
SAR ADC
SDO1
SDO2
SDO3
SDO4
SDO5
SDO6
SDO7
SDO8
CLKOUT
SCK
CNV
AAIINN77+– S/H
AAIINN88+– S/H
MUX
16-BIT
SAR ADC
REF REFOUT1 REFOUT2 REFOUT3 REFOUT4
232016 TA01a
1µF 10µF 10µF 10µF 10µF
SAMPLE
CLOCK
For more information www.linear.com/LTC2320-16
32k
IN
Point
FFT
fIN =
fSMPL =
500kHz
1.5Msps,
0 SNR = 82.2dB
–20
THD = –91.2dB
SINAD = 81.8dB
SFDR = 94.7dB
–40
–60
–80
–100
–120
–140
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7
FREQUENCY (MHz)
232016 TA01b
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1
1 page  
LTC2320-16
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
VDD
IVDD
CMOS I/O Mode
OVDD
IOVDD
INAP
ISLEEP
PD_3.3V
PD_5V
LVDS I/O Mode
OVDD
IOVDD
INAP
ISLEEP
PD_3.3V
PD_5V
PARAMETER
Supply Voltage
Supply Current
CONDITIONS
5V Operation
3.3V Operation
1.5Msps Sample Rate (IN+ = IN– = 0V)
CMOS/LVDS = GND
Supply Voltage
Supply Current
Nap Mode Current
Sleep Mode Current
Power Dissipation
Power Dissipation
1.5Msps Sample Rate (CL = 5pF)
Conversion Done (IVDD)
Sleep Mode (IVDD + IOVDD)
NVDaDp
= 3.3V,
Mode
1.5Msps
Sample
Rate
Sleep Mode
VDD = 5V, 1.5Msps Sample Rate
Nap Mode
Sleep Mode
CMOS/LVDS = OVDD, OVDD = 2.5V
Supply Voltage
Supply Current
Nap Mode Current
Sleep Mode Current
Power Dissipation
1.5Msps Sample Rate (CL = 5pF, RL = 100Ω)
Conversion Done (IVDD)
Sleep Mode (IVDD + IOVDD)
VDD = 3.3V, 1.5Msps Sample Rate
Nap Mode
Sleep Mode
Power Dissipation
NVDaDp
= 5V, 1.5Msps
Mode
Sample
Rate
Sleep Mode
MIN
l 4.75
l 3.13
l
l 1.71
l
l
l
l
l
l
l
l
l
l 2.37
l
l
l
l
l
l
l
l
l
TYP MAX UNITS
5.25 V
3.47 V
31 39
mA
2.63
4.4 8
5.3 6.9
20 110
102 133
18 22.7
20 355
162 210
27 34.4
30 525
V
mA
mA
µA
mW
mW
µW
mW
mW
µW
2.63
26 38
5.3 6.9
20 110
151 248
52 61.5
80 355
214 300
52 73
30 525
V
mA
mA
µA
mW
mW
µW
mW
mW
µW
For more information www.linear.com/LTC2320-16
232016fb
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5 Page 
PIN FUNCTIONS
REFBUFEN (Pin 43): Reference Buffer Output Enable. Tie
to VDD when using the internal reference. Tie to ground
to disable the internal REFOUT1–4 buffers for use with
external voltage references. This pin has a 500k internal
pull-up to VDD.
REFOUT4 (Pin 45): Reference Buffer 4 Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to GND and should be decoupled closely to the
pin with a 10µF (X5R, 0805 size) ceramic capacitor. The
internal buffer driving this pin may be disabled by ground-
ing the REFBUFEN pin. If the buffer is disabled, an external
reference may drive this pin in the range of 1.25V to 5V.
AFuINll8-+s,cAalIeN8r–a(nPgiens(A4I8N,84+7–):
Analog Differential Input Pins.
AIN8–) is ±REFOUT4 voltage.
These pins can be driven from VDD to GND.
FAuINll7-+s,cAalIeN7r–a(nPgiens(A5I1N,75+0–):
Analog Differential Input Pins.
AIN7–) is ±REFOUT4 voltage.
These pins can be driven from VDD to GND.
Exposed Pad (Pin 53): Ground. Solder this pad to ground.
CMOS DATA OUTPUT OPTION (CMOS/LVDS = LOW)
SDO1 (Pin 27): CMOS Serial Data Output for ADC Chan-
nel 1. The conversion result is shifted MSB first on each
falling edge of SCK in SDR mode and each SCK edge in
DDR mode. 16 SCK edges are required for 16-bit conver-
sion data to be read from AIN1 on SDO1 in SDR mode,
8 SCK edges in DDR mode. Supplying more clocks will
yield data from subsequent channels (CH2, CH3, CH4,
CH5, CH6, CH7, CH8).
SDO2 (Pin 28): CMOS Serial Data Output for ADC Chan-
nel 2. The conversion result is shifted MSB first on each
falling edge of SCK in SDR mode and each SCK edge in
DDR mode. 16 SCK edges are required for 16-bit conver-
sion data to be read from AIN2 on SDO2 in SDR mode,
8 SCK edges in DDR mode. Supplying more clocks will
yield data from subsequent channels (CH3, CH4, CH5,
CH6, CH7, CH8, CH1).
LTC2320-16
SDO3 (Pin 29): CMOS Serial Data Output for ADC Chan-
nel 3. The conversion result is shifted MSB first on each
falling edge of SCK in SDR mode and each SCK edge in
DDR mode. 16 SCK edges are required for 16-bit conver-
sion data to be read from AIN3 on SDO3 in SDR mode,
8 SCK edges in DDR mode. Supplying more clocks will
yield data from subsequent channels (CH4, CH5, CH6,
CH7, CH8, CH1, CH2).
SDO4 (Pin 30): CMOS Serial Data Output for ADC Chan-
nel 4. The conversion result is shifted MSB first on each
falling edge of SCK in SDR mode and each SCK edge in
DDR mode. 16 SCK edges are required for 16-bit conver-
sion data to be read from AIN4 on SDO4 in SDR mode,
8 SCK edges in DDR mode. Supplying more clocks will
yield data from subsequent channels (CH5, CH6, CH7,
CH8, CH1, CH2, CH3).
CLKOUT (Pin 33): Serial Data Clock Output. CLKOUT
provides a skew-matched clock to latch the SDO output
at the receiver (FPGA). The logic level is determined by
OVDD. This pin echoes the input at SCK with a small delay.
CLKOUTEN (Pin 34): CLKOUT can be disabled by tying
Pin 34 to OVDD for a small power savings. If CLKOUT is
used, ground this pin.
SDO5 (Pin 35): CMOS Serial Data Output for ADC Chan-
nel 5. The conversion result is shifted MSB first on each
falling edge of SCK in SDR mode and each SCK edge in
DDR mode. 16 SCK edges are required for 16-bit conver-
sion data to be read from AIN5 on SDO5 in SDR mode,
8 SCK edges in DDR mode. Supplying more clocks will
yield data from subsequent channels (CH6, CH7, CH8,
CH1, CH2, CH3, CH4).
SDO6 (Pin 36): CMOS Serial Data Output for ADC Chan-
nel 6. The conversion result is shifted MSB first on each
falling edge of SCK in SDR mode and each SCK edge in
DDR mode. 16 SCK edges are required for 16-bit conver-
sion data to be read from AIN6 on SDO6 in SDR mode,
8 SCK edges in DDR mode. Supplying more clocks will
yield data from subsequent channels (CH7, CH8, CH1,
CH2, CH3, CH4, CH5).
For more information www.linear.com/LTC2320-16
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC2320-16.PDF ] | |
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