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What is LTC2320-12?

This electronic component, produced by the manufacturer "Linear Technology", performs the same function as "1.5Msps/Ch Simultaneous Sampling ADC".


LTC2320-12 Datasheet PDF - Linear Technology

Part Number LTC2320-12
Description 1.5Msps/Ch Simultaneous Sampling ADC
Manufacturers Linear Technology 
Logo Linear Technology Logo 


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Features
nn 1.5Msps/Ch Throughput Rate
nn Eight Simultaneously Sampling Channels
nn Guaranteed 12-Bit, No Missing Codes
nn 8VP-P Differential Inputs with Wide Input
Common Mode Range
nn 77dB SNR (Typ) at fIN = 500kHz
nn –90dB THD (Typ) at fIN = 500kHz
nn Guaranteed Operation to 125°C
nn Single 3.3V or 5V Supply
nn Low Drift (20ppm/°C Max) 2.048V or 4.096V
Internal Reference
nn 1.8V to 2.5V I/O Voltages
nn CMOS or LVDS SPI-Compatible Serial I/O
nn Power Dissipation 20mW/Ch (Typ)
nn Small 52-Lead (7mm × 8mm) QFN Package
Applications
nn High Speed Data Acquisition Systems
nn Communications
nn Remote Data Acquisition
nn Imaging
nn Optical Networking
nn Automotive
nn Multiphase Motor Control
LTC2320-12
Octal, 12-Bit + Sign,
1.5Msps/Ch Simultaneous
Sampling ADC
Description
The LTC®2320-12 is a low noise, high speed octal 12‑bit
+ sign successive approximation register (SAR) ADC with
differential inputs and wide input common mode range.
Operating from a single 3.3V or 5V supply, the LTC2320‑12
has an 8VP-P differential input range, making it ideal for
applications which require a wide dynamic range with
high common mode rejection. The LTC2320-12 achieves
±0.25LSB INL typical, no missing codes at 12 bits and
77dB SNR.
The LTC2320-12 has an onboard low drift (20ppm/°C max)
2.048V or 4.096V temperature-compensated reference.
The LTC2320-12 also has a high speed SPI-compatible
serial interface that supports CMOS or LVDS. The fast
1.5Msps per channel throughput with no latency makes
the LTC2320-12 ideally suited for a wide variety of high
speed applications. The LTC2320-12 dissipates only 20mW
per channel and offers nap and sleep modes to reduce the
power consumption to 26μW for further power savings
during inactive periods.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
Typical Application
3.3V OR 5V
10µF
1µF
1.8V TO 2.5V
TRUE DIFFERENTIAL INPUTS
NO CONFIGURATION REQUIRED
IN+, IN
ARBITRARY
VDD
DIFFERENTIAL
VDD
0V 0V
BIPOLAR
VDD
UNIPOLAR
VDD
0V 0V
EIGHT SIMULTANEOUS
SAMPLING CHANNELS
AAIINN11+S/H
AAIINN22+S/H
MUX
VDD GND
12-BIT
+ SIGN
SAR ADC
GND OVDD
CMOS/LVDS
SDR/DDR
REFBUFEN
AAIINN33+S/H
AAIINN44+S/H
AAIINN55+S/H
AAIINN66–+ S/H
12-BIT
MUX + SIGN
SAR ADC
LTC2320-12
12-BIT
MUX + SIGN
SAR ADC
SDO1
SDO2
SDO3
SDO4
SDO5
SDO6
SDO7
SDO8
CLKOUT
SCK
CNV
AAIINN77+S/H
AAIINN88+S/H
MUX
12-BIT
+ SIGN
SAR ADC
REF REFOUT1 REFOUT2 REFOUT3 REFOUT4
232012 TA01a
1µF
10µF
10µF
10µF 10µF
SAMPLE
CLOCK
For more information www.linear.com/LTC2320-12
32k Point FFT fSMPL = 1.5Msps,
fIN =S5M0P0LkHz
IN
0 SNR = 78.4dB
–20
THD = –90.9dB
SINAD = 78.2dB
SFDR = 95.2dB
–40
–60
–80
–100
–120
–140
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7
FREQUENCY (MHz)
232012 TA01b
232012fa
1

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LTC2320-12 equivalent
LTC2320-12
Power Requirements The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
VDD
IVDD
CMOS I/O Mode
OVDD
IOVDD
INAP
ISLEEP
PD_3.3V
PD_5V
LVDS I/O Mode
OVDD
IOVDD
INAP
ISLEEP
PD_3.3V
PD_5V
PARAMETER
Supply Voltage
Supply Current
CONDITIONS
5V Operation
3.3V Operation
1.5Msps Sample Rate (IN+ = IN= 0V)
CMOS/LVDS = GND
Supply Voltage
Supply Current
Nap Mode Current
Sleep Mode Current
Power Dissipation
Power Dissipation
1.5Msps Sample Rate (CL = 5pF)
Conversion Done (IVDD)
Sleep Mode (IVDD + IOVDD)
NVDaDp
= 3.3V,
Mode
1.5Msps
Sample
Rate
Sleep Mode
VDD = 5V, 1.5Msps Sample Rate
Nap Mode
Sleep Mode
CMOS/LVDS = OVDD, OVDD = 2.5V
Supply Voltage
Supply Current
Nap Mode Current
Sleep Mode Current
Power Dissipation
1.5Msps Sample Rate (CL = 5pF, RL = 100Ω)
Conversion Done (IVDD)
Sleep Mode (IVDD + IOVDD)
VDD = 3.3V, 1.5Msps Sample Rate
Nap Mode
Sleep Mode
Power Dissipation
NVDaDp
= 5V, 1.5Msps
Mode
Sample
Rate
Sleep Mode
MIN
l 4.75
l 3.13
l
l 1.71
l
l
l
l
l
l
l
l
l
l 2.37
l
l
l
l
l
l
l
l
l
TYP MAX UNITS
5.25 V
3.47 V
31 38
mA
2.63
4.4 7
5.3 6.2
20 110
102 130
18 266
20 355
162 208
27 31.2
30 525
V
mA
mA
µA
mW
mW
µW
mW
mW
µW
2.63
26 34
5.3 6.2
20 110
151 196
52 60
80 355
214 275
51 685
30 525
V
mA
mA
µA
mW
mW
µW
mW
mW
µW
A DC Timing Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL PARAMETER
fSMPL
Maximum Sampling Frequency
tCYC Time Between Conversions
tCONV
Conversion Time
tCNVH
CNV High Time
tACQUISITION Sampling Aperture
tWAKE
REFOUT1,2,3,4 Wake-Up Time
CMOS I/O Mode, SDR
tSCK
tSCKH
tSCKL
tHSDO_SDR
tDSCKCLKOUT
SCK Period
SCK High Time
SCK Low Time
SDO Data Remains Valid Delay from CLKOUT
SCK to CLKOUT Delay
CONDITIONS
(Note 11) tCYC = tCNVH + tCONV + tREADOUT
(Note 11) tACQUISITION = tCYC – tCONV
CREFOUT1,2,3,4 = 10µF
CMOS/LVDS = GND, SDR/ DDR = GND
(Note 13)
CL = 5pF (Note 12)
(Note 12)
l
l
l
l
l
l
l
l
l
MIN
0.667
30
9.1
4.1
4.1
0
2
TYP MAX UNITS
1.5 Msps
1000 µs
450 ns
ns
215 ns
50 ms
ns
ns
ns
1.5 ns
4.5 ns
For more information www.linear.com/LTC2320-12
232012fa
5


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Part Details

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