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What is MPC9773?

This electronic component, produced by the manufacturer "Freescale Semiconductor", performs the same function as "3.3 V 1:12 LVCMOS PLL Clock Generator".


MPC9773 Datasheet PDF - Freescale Semiconductor

Part Number MPC9773
Description 3.3 V 1:12 LVCMOS PLL Clock Generator
Manufacturers Freescale Semiconductor 
Logo Freescale Semiconductor Logo 


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Freescale Semiconductor
Technical Data
MPC9773
Rev 5, 08/2005
3.3 V 1:12 LVCMOS PLL Clock
Generator
MPC9773
The MPC9773 is a 3.3 V compatible, 1:12 PLL based clock generator targeted
for high-performance low-skew clock distribution in mid-range to high-
performance networking, computing, and telecom applications. With output
frequencies up to 240 MHz and output skews less than 250 ps the device meets
the needs of the most demanding clock applications.
Features
• 1:12 PLL based low-voltage clock generator
• 3.3 V power supply
• Internal power-on reset
• Generates clock signals up to 242.5 MHz
• Maximum output skew of 250 ps
• Differential PECL reference clock input
• Two LVCMOS PLL reference clock inputs
• External PLL feedback supports zero-delay capability
• Various feedback and output dividers (refer to Application Section)
• Supports up to three individual generated output clock frequencies
• Synchronous output clock stop circuitry for each individual output for power
down support
• Drives up to 24 clock lines
• Ambient temperature range -40°C to +85°C
• Pin and function compatible to the MPC973
• 52-lead Pb-free package available
3.3 V 1:12 LVCMOS
PLL CLOCK GENERATOR
FA SUFFIX
52-LEAD LQFP PACKAGE
CASE 848D-03
AE SUFFIX
52-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 848D-03
Functional Description
The MPC9773 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
MPC9773 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The
reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match
the VCO frequency range. The MPC9773 features an extensive level of frequency programmability between the 12 outputs as
well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and 8:3.
The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the
feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference
versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addi-
tion, the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a non-
binary factor. The MPC9773 also supports the 180° phase shift of one of its output banks with respect to the other output banks.
The QSYNC outputs reflect the phase relationship between the QA and QC outputs and can be used for the generation of system
baseline timing signals.
The REF_SEL pin selects the LVPECL or the LVCMOS compatible inputs as the reference clock signal. Two alternative
LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass con-
figuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers,
bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics
do not apply.
The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the
MPC9773. The MPC9773 has an internal power-on reset.
The MPC9773 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except PCLK) accept
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission
lines. For series terminated transmission lines, each of the MPC9773 outputs can drive one or two traces, giving the devices an
effective fanout of 1:24. The device is pin and function compatible to the MPC973 and is packaged in a 52-lead LQFP package.
© Freescale Semiconductor, Inc., 2005. All rights reserved.

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MPC9773 equivalent
Table 7. General Specifications
Symbol
Characteristics
VTT Output Termination Voltage
MM ESD Protection (Machine Model)
HBM ESD Protection (Human Body Model)
LU Latch-Up Immunity
CPD Power Dissipation Capacitance
CIN Input Capacitance
Min
200
2000
200
Typ
VCC ÷ 2
12
4.0
Max Unit Condition
V
V
V
mA
pF Per output
pF Inputs
Table 8. Absolute Maximum Ratings(1)
Symbol
Characteristics
Min Max Unit Condition
VCC
VIN
VOUT
IIN
IOUT
TS
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
–0.3
–0.3
–0.3
–65
3.9
VCC + 0.3
VCC + 0.3
±20
±50
125
V
V
V
mA
mA
°C
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 9. DC Characteristics (VCC = 3.3 V ± 5%, TA = -40°C to 85°C)
Symbol
Characteristics
Min Typ Max Unit Condition
VCC_PLL
VIH
VIL
VPP
VCMR
VOH
VOL
PLL Supply Voltage
Input High Voltage
Input Low Voltage
Peak-to-Peak Input Voltage
Common Mode Range(1)
Output High Voltage
Output Low Voltage
ZOUT
IIN
ICC_PLL
ICCQ
Output Impedance
Input Current(3)
Maximum PLL Supply Current
Maximum Quiescent Supply Current
3.0
2.0
PCLK, PCLK
PCLK, PCLK
250
1.0
2.4
14 – 17
8.0
VCC
VCC + 0.3
0.8
VCC – 0.6
0.55
0.30
±200
13.5
35
V LVCMOS
V LVCMOS
V LVCMOS
mV LVPECL
V LVPECL
V IOH = –24 mA(2)
V IOL = 24 mA
V IOL = 12 mA
µA VIN = VCC or GND
mA VCC_PLL Pin
mA All VCC Pins
1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (DC) specification.
2. The MPC9773 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines.
3. Inputs have pull-down resistors affecting the input current.
Advanced Clock Drivers Device Data
Freescale Semiconductor
MPC9773
5


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