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Número de pieza | L24C128A | |
Descripción | 128K bits EEPROM | |
Fabricantes | LIZE | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de L24C128A (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
No Preview Available ! Shenzhen LIZE Electronic Technology Co., Ltd
SPECIFICATION
L24C128A
128Kbits(16384×8)
1 page Figure 1. Data Validity
Figure 2. Start and Stop Definition
Figure 3. Output Acknowledge
3. Device Addressing
The 128K EEPROM devices all require an 8-bit device address word following a start condition to
enable the chip for a read or write operation (see Figure 4)
The device address word consists of a mandatory "1", "0" sequence for the first four most significant
bits as shown. This is common to all the Serial EEPROM devices.
The 128K EEPROM uses A2, A1 and A0 device address bits to allow as much as eight devices on the
same bus. These 3 bits must be compared to their corresonding hardwired input pins. The A2, A1 and
A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are
allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated
ShBenLz2h4eCn12L8IZAE. ERlevc1tr.9onic Technology CO., Ltd
Date:26.Sep.2016 4
Page: 5 of 15
5 Page Bus Timing
Figure 10: SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
Figure 11: SCL: Serial Clock, SDA: Serial Data I/O
Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the
internal clear/write cycle.
BShLe2n4Czh1e2n8AL.IZREeEvl1e.c9tronic Technology CO., Ltd
Date:26.Sep.2016 10
Page: 11 of 15
11 Page |
Páginas | Total 15 Páginas | |
PDF Descargar | [ Datasheet L24C128A.PDF ] |
Número de pieza | Descripción | Fabricantes |
L24C128 | EEPROM | LIZE |
L24C128A | 128K bits EEPROM | LIZE |
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