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What is MPC973?

This electronic component, produced by the manufacturer "Motorola Semiconductors", performs the same function as "LOW VOLTAGE PLL CLOCK DRIVER".


MPC973 Datasheet PDF - Motorola Semiconductors

Part Number MPC973
Description LOW VOLTAGE PLL CLOCK DRIVER
Manufacturers Motorola Semiconductors 
Logo Motorola Semiconductors Logo 


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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low Voltage PLL Clock Driver
The MPC972/973 are 3.3V compatible, PLL based clock driver
devices targeted for high performance CISC or RISC processor based
systems. With output frequencies of up to 125MHz and skews of 550ps
the MPC972/973 are ideally suited for most synchronous systems. The
devices offer twelve low skew outputs plus a feedback and sync output for
added flexibility and ease of system implementation.
Fully Integrated PLL
Output Frequency up to 125MHz
Compatible with PowerPCand PentiumMicroprocessors
TQFP Packaging
3.3V VCC
± 100ps Typical Cycle–to–Cycle Jitter
MPC972
MPC973
LOW VOLTAGE
PLL CLOCK DRIVER
The MPC972/973 features an extensive level of frequency
programmability between the 12 outputs as well as the input vs output
relationships. Using the select lines output frequency ratios of 1:1, 2:1,
3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 6:1 and 6:5 between outputs can be
realized by pulsing low one clock edge prior to the coincident edges of the
Qa and Qc outputs. The Sync output will indicate when the coincident
rising edges of the above relationships will occur. The selectability of the
feedback frequency is independent of the output frequencies, this allows
for very flexible programming of the input reference vs output frequency
relationship. The output frequencies can be either odd or even multiples
of the input reference. In addition the output frequency can be less than
the input frequency for applications where a frequency needs to be
reduced by a non–binary factor. The Power–On Reset ensures proper
programming if the frequency select pins are set at power up. If the
fselFB2 pin is held high, it may be necessary to apply a reset after
power–up to ensure synchronization between the QFB output and the
other outputs. The internal power–on reset is designed to provide this
function, but with power–up conditions being system dependent, it is
difficult to guarantee. All other conditions of the fsel pins will automatically
synchronize during PLL lock acquisition.
FA SUFFIX
52–LEAD TQFP PACKAGE
CASE 848D-03
The MPC972/973 offers a very flexible output enable/disable scheme. This enable/disable scheme helps facilitate system
debug as well as provide unique opportunities for system power down schemes to meet the requirements of “green” class
machines. The MPC972 allows for the enabling of each output independently via a serial input port. When disabled or “frozen”
the outputs will be locked in the “LOW” state, however the internal state machines will continue to run. Therefore when “unfrozen”
the outputs will activate synchronous and in phase with those outputs which were not frozen. The freezing and unfreezing of
outputs occurs only when they are already in the “LOW” state, thus the possibility of runt pulse generation is eliminated. A
power-on reset will ensure that upon power up all of the outputs will be active. Note that all of the control inputs on the
MPC972/973 have internal pull–up resistors.
The MPC972/973 is fully 3.3V compatible and requires no external loop filter components. All inputs accept LVCMOS/LVTTL
compatible levels while the outputs provide LVCMOS levels with the capability to drive 50transmission lines. For series
terminated lines each MPC972/973 output can drive two 50lines in parallel thus effectively doubling the fanout of the device.
The MPC972/973 can consume significant power in some configurations. Users are encouraged to review Application Note
AN1545/D in the Timing Solutions book (BR1333/D) for a discussion on the thermal issues with the MPC family of clock drivers.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
8/97
© Motorola, Inc. 1997
1
REV 1

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MPC973 equivalent
MPC972 MPC973
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min Max Unit
VCC
Supply Voltage
–0.3 4.6 V
VI Input Voltage
–0.3
VDD + 0.3
V
IIN Input Current
±20 mA
TStor
Storage Temperature Range
–40 125 °C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not
implied.
DC CHARACTERISTICS (Note 4.; TA = 10° to 70°C; VCC = 3.3V ±5%)
Symbol
Characteristic
Min Typ Max Unit
Condition
VIH Input HIGH Voltage
2.0 3.6 V
VIL Input LOW Voltage
0.8 V
VPP
Peak–to–Peak Input Voltage PECL_CLK
300
1000
mV
VCMR
Common Mode Range
PECL_CLK VCC–2.0
VCC–0.6
Note 1.
VOH
Output HIGH Voltage
2.4
V IOH = –20mA (Note 2.)
VOL
Output LOW Voltage
0.5 V IOL = 20mA (Note 2.)
IIN Input Current
±120
µA Note 3.
ICC Maximum Quiescent Supply Current
190 215 mA All VCC PIns
ICCA
Analog VCC Current
15 20 mA
CIN Input Capacitance
4 pF
Cpd Power Dissipation Capacitance
25 pF Per Output
1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within
the VCMR range and the input lies within the VPP specification.
2. The MPC972/973 outputs can drive series or parallel terminated 50(or 50to VCC/2) transmission lines on the incident edge (see Applications
Info section).
3. Inputs have pull–up/pull–down resistors which affect input current.
4. Special thermal handling may be required in some configurations.
PLL INPUT REFERENCE CHARACTERISTICS (TA = 10° to 70°C)
Symbol
Characteristic
Min Max Unit Condition
tr, tf TCLK Input Rise/Falls
3.0 ns
fref Reference Input Frequency
Note 5. 100, Note 5. MHz Note 5.
frefDC
Reference Input Duty Cycle
25 75 %
txtal Crystal Oscillator Frequency
10 25 MHz Note 6.
5. Maximum input reference frequency is limited by the VCO lock range and the feedback divider or 100MHz, minimum input reference frequency
is limited by the VCO lock range and the feedback divider.
6. See Applications Info section for more crystal information.
TIMING SOLUTIONS
BR1333 — Rev 6
5
MOTOROLA


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