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PDF MT4LSDT464A Data sheet ( Hoja de datos )
| Número de pieza | MT4LSDT464A | |
| Descripción | 32MB SDRAM Unbuffered DIMM | |
| Fabricantes | Micron | |
| Logotipo |  |
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32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Features
SDRAM Unbuffered DIMM (UDIMM)
MT4LSDT464A – 32MB
MT4LSDT864A(I) – 64MB
MT4LSDT1664A(I) – 128MB
For component data sheets, refer to Micron’s Web site: www.micron.com
Features
• 168-pin, dual in-line memory module (DIMM)
• PC100- and PC133-compliant
• Unbuffered
• 32MB (4 Meg x 64)2, 64MB (8 Meg x 64),
128MB (16 Meg x 64)
• Single +3.3V power supply
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal SDRAM banks for hiding row access/
precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes CONCURRENT AUTO
PRECHARGE and auto refresh modes
• Self refresh mode: 64ms, 4,096-cycle refresh
for 32MB and 64MB; 64ms, 8,192-cycle refresh
for 128MB
• LVTTL-compatible inputs and outputs
• Serial presence-detect (SPD)
• Gold edge contacts
Figure 1: 168-Pin DIMM (MO-161)
Standard 25.4mm (1.0in)
Options
• Package
– 168-pin DIMM (standard)
– 168-pin DIMM (Pb-free)
• Operating temperature range
– Commercial (0°C to +65°C)
– Industrial (–40°C to +85°C)1, 3
• Frequency/CAS Latency
– 7.5ns (133 MHz)/CL = 2
– 7.5ns (133 MHz)/CL = 3
– 8ns (100 MHz)/CL = 22
• PCB
– Standard 25.40mm (1.0in)
Marking
G
Y
None
I
-13E
-133
-10E
Notes: 1. Contact Micron for product availability.
2. Not recommended for new designs.
3. Industrial temperature option available in
-133 MHz only.
Table 1:
Key Timing Parameters
CL = CAS (READ) latency
Speed Grade
-13E
-133
-10E2
Industry
Nomenclature
PC133
PC133
PC100
Access Time
CL = 2
5.4ns
–
9ns
CL = 3
–
5.4ns
7.5ns
Setup Time
-13E
-133
-10E
Hold Time
133 MHz
133 MHz
100 MHz
PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3
SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Pin Assignments and Descriptions
Table 5:
Pin Descriptions (Continued)
Pins may not correlate with symbols; refer to Table 4 on page 3 for more information
Pin Numbers
6, 18, 26, 40, 41, 49, 59,
73, 84, 90, 102, 110, 124,
133, 143, 157, 168
1, 12, 23, 32, 43, 54, 64,
68, 78, 85, 96, 107, 116,
127, 138, 148, 152, 162
21, 22, 52, 53, 105, 106,
114, 125, 129, 132, 163
24, 25, 31, 44, 48, 50, 51,
61, 62, 63, 80, 81, 108,
109, 126 (32MB, 64MB),
134, 135, 145–147, 164
Symbol
VDD
VSS
DNU
NC
Type
Supply
Description
Power supply: +3.3V ±0.3V.
Supply
Ground.
– Do not use: These pins are not used on these modules, but
are assigned pins on other modules in this product family.
– Not connected: These pins are not connected on these
modules.
PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3
SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
5 Page 
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Mode Register Definition
Table 6: Burst Definition Table
Order of Accesses Within a Burst
Burst Length
2
4
8
Full page (y)
Starting Column Address
Type = Sequential
Type = Interleaved
A0
0 0-1
0-1
1
A1 A0
1-0
1-0
00
0-1-2-3
0-1-2-3
01
1-2-3-0
1-0-3-2
10
11
A2 A1 A0
000
001
010
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
011
3-4-5-6-7-0-1-2
3-4-5-6-7-0-1-2
100
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
101
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
110
111
n = A0–Ai
(location
0–y)
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1,
Cn + 2, Cn + 3,
Cn + 4. . . Cn - 1,
Cn . . .
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not supported
Notes:
1. For full-page accesses: y = 256 (32MB); y = 512 (64MB/128MB).
2. For BL = 2, A1–Ai select the block-of-two burst; A0 selects the starting column within the
block.
3. For BL = 4, A2–Ai select the block-of-four burst; A0–A1 select the starting column within the
block.
4. For BL = 8, A3–Ai select the block-of-eight burst; A0–A2 select the starting column within
the block.
5. For a full-page burst, the full row is selected and A0–Ai select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the following
access wraps within the block.
7. For BL = 1, A0–Ai select the unique column to be accessed, and mode register bit M3 is
ignored.
8. i = 7 for 32MB; i = 8 for 64MB and 128MB.
PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3
SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
11 Page | ||
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| PDF Descargar | [ Datasheet MT4LSDT464A.PDF ] | |
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