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PDF MT18VDVF6472D Data sheet ( Hoja de datos )
| Número de pieza | MT18VDVF6472D | |
| Descripción | 512MB DDR SDRAM VLP Registered DIMM | |
| Fabricantes | Micron | |
| Logotipo |  |
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512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Features
DDR SDRAM VLP Registered DIMM
MT18VDVF6472D – 512MB
MT18VDVF12872D – 1GB
For the latest data sheet, refer to Micron’s Web site: www.micron.com/products/modules
Features
• 184-pin, very low profile dual in-line memory
module (VLP DIMM)
• Fast data transfer rates: PC2100 or PC2700
• Utilizes 266 MT/s and 333 MT/s DDR SDRAM
components
• Registered inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to reduce loading
• Supports ECC error detection and correction
• 512MB (64 Meg x 72) and 1GB (128 Meg x 72)
• VDD = VDDQ = +2.5V
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto refresh and self refresh modes
• 7.8125µs maximum average periodic refresh
interval
• Serial presence detect (SPD) with EEPROM
• Programmable READ CAS latency
• Gold edge contacts
• Dual rank
Figure 1: 184-Pin VLP DIMM (MO-206)
Very Low Profile Height 0.72in (18.29mm)
Options
Marking
• Package
184-pin DIMM (standard)
184-pin DIMM (lead-free)1
• Memory clock, speed, CAS latency2
6ns (166MHz), 333 MT/s, CL = 2.5
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2.5
• PCB height
Very Low-Profile 0.72in (18.29mm)1
G
Y
-335
-2621
-26A1
-265
Notes:1. Contact Micron for product availability.
2. CL = CAS (READ) latency; registered mode
adds one clock cycle to CL.
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C64_128x72D_1.fm - Rev. A 8/05 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Table 19:
Table 20:
Table 21:
Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Part Numbers and Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Burst Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
CAS Latency Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Commands Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
DM Operation Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
AC Input Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
IDD Specifications and Conditions – 512MB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
IDD Specifications and Conditions – 1GB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Capacitance (512MB only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .20
Register Timing Requirements and Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
PLL Clock Driver Timing Requirements and Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . .30
EEPROM Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
EEPROM Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Serial Presence-Detect EEPROM DC Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Serial Presence-Detect EEPROM AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Serial Presence-Detect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C64_128x72DLOT.fm - Rev. A 8/05 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
5 Page 
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Mode Register Definition
various SDRAM organizations and timing parameters. The remaining 128 bytes of stor-
age are available for use by the customer. System READ/WRITE operations between the
master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C
bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on
the module, permanently disabling hardware write protect.
Mode Register Definition
The mode register is used to define the specific mode of operation of DDR SDRAM
devices. This definition includes the selection of a burst length, a burst type, a CAS
latency and an operating mode, as shown in Figure 4, "Mode Register Definition Dia-
gram," on page 12. The mode register is programmed via the MODE REGISTER SET
command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is
programmed again or the device loses power (except for bit A8, which is self-clearing).
Reprogramming the mode register will not alter the contents of the memory, provided it
is performed correctly. The mode register must be loaded (reloaded) when all device
banks are idle and no bursts are in progress, and the controller must wait the specified
time before initiating the subsequent operation. Violating either of these requirements
will result in unspecified operation.
Mode register bits A0–A2 specify the burst length, A3 specifies the type of burst (sequen-
tial or interleaved), A4–A6 specify the CAS latency, and A7–A12 specify the operating
mode.
Burst Length
Read and write accesses to DDR SDRAM devices are burst oriented, with the burst
length being programmable, as shown in Figure 4, "Mode Register Definition Diagram,"
on page 12. The burst length determines the maximum number of column locations
that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8
locations are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A1–Ai when the burst length is set to two, by A2–Ai when the burst
length is set to four and by A3–Ai when the burst length is set to eight (where Ai is the
most significant column address bit for a given configuration. See Note 5 of Table 5,
"Burst Definition Table," on page 13, for Ai values). The remaining (least significant)
address bit(s) is (are) used to select the starting location within the block. The pro-
grammed burst length applies to both READ and WRITE bursts.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type
and the starting column address, as shown in Table 5, "Burst Definition Table," on
page 13.
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
11 Page | ||
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| PDF Descargar | [ Datasheet MT18VDVF6472D.PDF ] | |
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