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PDF SM5964 Data sheet ( Hoja de datos )
| Número de pieza | SM5964 | |
| Descripción | 8-Bit Micro-controller | |
| Fabricantes | SyncMOS | |
| Logotipo |  |
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SyncMOS Technologies Inc.
SM5964
July 2002
8 - Bit Micro-controller
Product List
SM5964C25, 25 MHz 64KB internal flash MCU
SM5964C40, 40 MHz 64KB internal flash MCU
Description
The SM5964 series product is an 8 - bit single chip
microcontroller with 64KB flash & 1K byte RAM embed-
ded. It has In-System Programming (ISP) function and
is a derivative of the 8052 microcontroller family. It has
5-channel SPWM build-in. User can access on-chip
expanded RAM with easier and faster way by its ‘bank
mapping direct addressing mode’ scheme. With its
hardware features and powerful instruction set, it’s
straight forward to make it a versatile and cost effective
controller for those applications which demand up to 32
I/O pins for PDIP package or up to 36 I/O pins for
PLCC/QFP package, or applications which need up to
64K byte flash memory either for program or for data or
mixed.
To program the on-chip flash memory, a commercial
writer is available to do it in parallel programming
method. The on-chip flash memory can be programmed
in either parallel or serial interface with its ISP feature.
Ordering Information
yywwv
SM5964ihhk
yy: year, ww:week
v: version identifier { , A, B, ...}
i: process identifier
hh: working clock in MHz {25, 40}
k: package type postfix {as below table}
Postfix
P
J
Q
Package
40L PDIP
44L PLCC
44L QFP
Pin/Pad
Configuration
page 2
page 2
page 2
Dimension
page 24
page 25
page 26
64KB ISP flash & 1KB RAM embedded
Features
Working voltage: 4.5V through 5.5V
General 8052 family compatible
12 clocks per machine cycle
64K byte on chip flash memory with In-System
Programming (ISP) capability
1024 byte on chip data RAM
Three 16 bit Timers/Counters
One Watch Dog Timer
Four 8-bit I/O ports for PDIP package
Four 8-bit I/O ports + one 4-bit I/O ports
for PLCC or QFP package
Full duplex serial channel
Bit operation instruction
Page free jumps
8-bit Unsigned Division
8-bit Unsigned Multiply
BCD arithmetic
Direct Addressing
Indirect Addressing
Nested Interrupt
Two priority level interrupt
A serial I/O port
Power save modes:
Idle mode and Power down mode
Code protection function
Low EMI (inhibit ALE)
Reset with address $0000 blank initiate ISP service program
ISP service program space configurable in N*512byte
(N=0 to 8) size
Bank mapping direct addressing mode for access on-chip
RAM
Five channel Specific PWM (SPWM) build-in with P1.3 ~ P1.7
Taiwan
4F, No. 1 Creation Road 1,
Science-based Industrial Park,
Hsinchu, Taiwan 30077
Website: http://www.syncmos.com.tw
Specifications subject to change without notice,contact your sales representatives for the most recent information.
TEL: 886-3-578-3344
886-3-579-2988
FAX: 886-3-579-2960
886-3-578-0493
1/28
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1 page  
SyncMOS Technologies Inc.
July 2002
SM5964
Special Function Register (SFR)
The address $80 to $FF can be accessed by direct addressing mode only.
Address $80 to $FF is SFR area.
The following table list the SFRs which are identical to general 8052 as well as SM5964 Extension SFRs.
$F8
$F0 B
ISPFAH ISPFAL ISPFD
ISPC
$E8
$E0 ACC
$D8 P4
$D0 PSW
$C8 T2CON
T2MOD
RCAP2L
RCAP2H
TL2
TH2
$C0
$B8 IP
SCONF
$B0 P3
$A8 IE
SPWMD4
$A0 P2
$98 SCON
$90 P1
SBUF
SPWMC
P1CON
SPWMD0
SPWMD1 SPWMD2
SPWMD3
WDTC
WDTKEY
$88 TCON
TMOD
TL0
TL1
TH0 TH1
$80 P0 SP DPL DPH
RCON DBANK PCON
Note: The text of SFRs with bold type characters are Extension Special Function Registers for SM5964
$FF
$F7
$EF
$E7
$DF
$D7
$CF
$C7
$BF
$B7
$AF
$A7
$9F
$97
$8F
$87
Addr
85H
86H
9BH
9FH
A3H
A4H
A5H
A6H
A7H
ACH
BFH
C9H
D8H
SFR Reset
7
6
5
RCON ******00
DBANK 0***0001 BSE
P1CON 00000*** SPWM4E SPWM3E SPWM2E
WDTC 0*0**000 WDTE
CLEAR
SPWMC ******00
SPWMD0 00H SPWMD0.4 SPWMD0.3 SPWMD0.2
SPWMD1 00H SPWMD1.4 SPWMD1.3 SPWMD1.2
SPWMD2 00H SPWMD2.4 SPWMD2.3 SPWMD2.2
SPWMD3 00H SPWMD3.4 SPWMD3.3 SPWMD3.2
SPWMD4 00H SPWMD4.4 SPWMD4.3 SPWMD4.2
SCONF 0****010 WDR
T2MOD ******00*
*
*
*
P4 ****1111
43
BS3
SPWM1E SPWM0E
SPWMD0.1 SPWMD0.0
SPWMD1.1 SPWMD1.0
SPWMD2.1 SPWMD2.0
SPWMD3.1 SPWMD3.0
SPWMD4.1 SPWMD4.0
**
P4.3
2
BS2
PS2
BRM0.2
BRM1.2
BRM2.2
BRM3.2
BRM4.2
ISPE
*
P4.2
1
RAMS1
BS1
PS1
FPDIV1
BRM0.1
BRM1.1
BRM2.1
BRM3.1
BRM4.1
OME
T2OE
P4.1
0
RAMS0
BS0
PS0
FPDIV0
BRM0.0
BRM1.0
BRM2.0
BRM3.0
BRM4.0
ALEI
DCEN
P4.0
Specifications subject to change without notice,contact your sales representatives for the most recent information.
5/28
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5 Page 
SyncMOS Technologies Inc.
July 2002
SM5964
The lock bit N function is different from the flash protect function. The flash erase function can erase all of the flash memory
except for the locked ISP service program space. If the flash not been protected, the content of ISP service program still
can be read. If the flash been protected, the overall content of flash program memory space including ISP service program
space can not be read.
3.3 Program the ISP Service Program
After Lock Bit N is set and ISP service program been programmed, the ISP service program memory will be protected
(locked) automatically. The lock bit N has its own program/erase timing. It is different from the flash memory program/erase
timing so the locked ISP service program can not be erased by flash erase function. If user need to erase the locked ISP
service program, he can do it by writer only. User can not change ISP service program when SM5964 was in system.
3.4 Initiate ISP Service Program
To initiate the ISP service program is to load the program counter (PC) with start address of ISP service program and exe-
cute it. There are two ways to do so:
(1) Blank reset. Hardware reset with first flash address blank ($0000=#FFH) will load the PC with start address of ISP ser-
vice program.
(2) Execute jump instruction can load the start address of the ISP service program to PC.
User can initiate general 8052 INT function to initiate the ISP service program. After ISP service program executed, user
need to reset the SM5964, either by hardware reset or by WDT, or jump to the address $0000 to re-start the firmware pro-
gram.
ISP Registers - ISPFAH, ISPFAL, ISPFD and ISPC
ISP Flash Address-High Register (ISPFAH, $F4)
Read:
Write:
Reset value:
bit-7
FA15
0
FA14
0
FA13
0
FA12
0
FA11
0
FA10
0
FA9
0
bit-0
FA8
0
FA15 ~ FA8: flash address-high for ISP function
ISP Flash Address-Low Register (ISPFAL, $F5)
bit-7 bit-0
Read:
Write:
FA7 FA6 FA5 FA4 FA3 FA2 FA1 FA0
Reset value:
0
0
0
0
0
0
0
0
FA7 ~ FA0: flash address-low for ISP function
The ISPFAH & ISPFAL provide the 16-bit flash memory address for ISP function. The flash memory address should not
include the ISP service program space address. If the flash memory address indicated by ISPFAH & ISPFAL registers
Specifications subject to change without notice,contact your sales representatives for the most recent information.
11/28
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PID 5964 07/02
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet SM5964.PDF ] | |
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