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PDF M5M5116P-15 Data sheet ( Hoja de datos )
| Número de pieza | M5M5116P-15 | |
| Descripción | 16K-Bit CMOS Static RAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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MITSUBISHI LSls
M5M5116P, -15
16384-BIT (2048-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5116P series of 2048-word by 8-bit asynchronous
silicon gate CMOS static RAM operates on a single 5V
power supply and is designed for easy use in applications
requiring battery backup.
Two chip select inputs are available: S2 provides the
minimum standby current with battery back-up while SI
enables high-speed memory access.
The series is packaged in a standard 24-pin plastic DI L
package.
FEATURES
Type name
Access time
(max)
M5M5116P-15
M5M5116P
150ns
200ns
S7 access
time
(max)
80ns
100n8
Current consumption
Active
(max)
Stand-by
(max)
SOmA
15,uA
• Single 5V power supply.
• External clock and refresh operation not required.
• Data can be held with 2V supply voltage.
• All inputs and outputs are directly TTL compatible.
• All outputs are 3-state with OR-tie capability.
• Easy expansion of memory capacity with chip select
signal.
• Common input/output for data pins.
APPLICATIONS
Battery drive, small-capacity memory units with battery
back-up
PIN CONFIGURATION (TOP VIEW)
A7 - 1
ADDRESS A4
INPUTS A3
Al
AI
Ao
DATA 001
1INPUTS/ J DOl
OUTPUTS
003
(DV) GND
Vcc(5V)
I23 - A8
I22 _ A9 ADDRESS INPUTS
21 - Vi \%~~i CONTROL
s;10 - CHIP SELECT INPUT
19 - AJOADDRESS INPUT
J8 - S, CHIP SELECT INPUT
DATA
INPUTS/
OUTPUTS
Outline 24 P4
FUNCTION
The M5M5116P series has a 2048-word by 8-bit configura-
tion. It operates on a single 5V supply and its inputs/
outputs are directly TTL compatible. Its completely static
circuitry obviates the need for external clock and refresh
operations and makes it very easy to use.
The data of the DQ pin are written when the address is
designated by address signals Ao - AlQ, the ~ and S2
signals turn low-level, and the W signal is set low.
When for the reading operation the W signal is set high,
BLOCK DIAGRAM
ADDRESS INPUTS
A9
A8
-----------------
2048-WORO
128 X 8-BIT RAM
1128 ROWS X
128 COLUMNS)
DATA
INPUTS/OUTPUTS
WRITE CONTROL INPUT
IICHIP SELECT INPUTS
~
s,
18»--~r;I-----------_--.J
' - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---.-J
• MITSUBISHI
"ELECTRIC
4-3
1 page  
MITSUBISHI LSls
M5M5116P, -15
16384-BIT (2048-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle (5 control)
tew
w
DO,-DOs
(DATA IN)
DO,-DOs
(DATA OUT)
Note 4
Test conditions
Input pulse level" 0.4 ~ 2.4V
Input pulse risetime and falltime: 10ns
Load 1 TTL, CL = 100pF
Reference level: 1.5V
tW(W)
tsu (01
DATA IN STABLE
Note 5: Hatching indicates the don't care inputs.
6' Writing is performed while S and Vi are in the
low-level overlap period.
7' The output is kept in the high-impedance state
when IN falls simultaneously with, or before, the
Sfalls
S" A reverse-phase signal should not be supplied when
DQ is in the output mode.
POWER-DOWN CHARACTERISTICS
Vee
S2
VCCIPD)
• MITSUBISHI
"'ELECTRIC
4-7
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet M5M5116P-15.PDF ] | |
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