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PDF MH6408AND-15 Data sheet ( Hoja de datos )
| Número de pieza | MH6408AND-15 | |
| Descripción | 512K-Bit DRAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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MITSUBISHI LSls
MH6408AND-15
S24 288-BIT(GS S3G-WORD BY 8-BIT)DYNAMIC RAM
DESCRIPTION
The MH6408AND is 65536 word x 8 bit dynamic RAM
and consists of eight industry standard 64K x 1 dynamic
RAMs in leadless chip carrier.
The mounting of leadless chip carriers on a ceramic single
in-line package provides any application where high den-
sities and large quantities of memory are required.
FEATURES
• Performance ranges
Type name
MH6408AND-15
Access time
~max)
~nsl
150
Cycle time
(min)
Insl
260
Power dissipation
Itypl
ImWI
1200
• Utilizes industry standard 64K RAMs in leadless chip
carriers
• 30 pins Single In-line Package
• Single +5V (±10%) supply operation
• Low standby power dissipation 176mW(max}
• Low operating power dissipation:
MH6408AND-15 1.9W (max)
• All inputs are directly TTL compatible
• All outputs are three-state and directly
• All outputs are three-state and directly TTL compatible
• Includes (0.22J,1F x 6) decoupling capacitors
• 128 refresh cycles (every 2ms) A7 Pin is not need for
refresh
APPLICATION
• Main memory unit for computers
• Refresh memory
PIN CONFIGURATION (TOP VIEW)
ADDRESS
INPUTS
DATA INPUT
DATA INPUT
DATA INPUT
DATA INPUT
DATA INPUT
DATA INPUT
DATA INPUT
DATA INPUT
DATA OUTPUT
DATA OUTPUT
DATA OUTPUT
DATA OUTPUT
DATA OUTPUT
DATA OUTPUT
DATA OUTPUT
DATA OUTPUT
!5VI
---Ao
-At
--A2
A3
-A4
--As
A6
-A7
-NC
Do
-D,
-D2
-D3
-D4
-Ds
-D6
-D7
-Qo
-Ql
-Q2
-Q3
-Q4
-Q5
-Q6
--Q7
Vee
~
~
,;cz..
c
G8
~
~
,~.
cz
);-
c
G15
16
~
~
~
~,z.
c
G23
~
~
,~.
,cz..
c
Outline 3085
BLOCK DIAGRAM
Do
1- 14
Qo
22 - IS
I
D2
23 - 16
Q2
24 - 17
25 - 18
DS
26 - 19
Qs D6
27 - 20
28 - 21
29
I
M5K4164AND/AD M5K4164AND/AD M5K4164AND/AD M5K4164AND/AD M5K4164AND/AD M5K4164AND/AD M5K4164AND/AD M5K4164AND/AD
1I
iI
I
I -~-J-jJ
2 -3-4
~-
RAS
-CAS
w-
Vee Vss
• .MITSUBISHI
"ELECTRIC
2-217
1 page  
MITSUBISHI LSls
MH640SAND-lS
524 288·BIT(65 536·WORD BY 8.BIT)DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Page-Mode Cycle)
(Ta=O-70°C, Vcc=5V±10%. Vss=ov. unless otherwise noted,See notes 5,6and 7)
Symbol
Parameter
tc RF
t W (RASH)
t W (RASU
I w(CASLi
t W(CASH)
I h (RAS-CAS)
t h (CAS- RAS)
td (CAS-RAS)
I d (RAS-CAS)
I SU(AA-AAS)
t SU(CA-CAS)
t h (AAS-AA)
'h (CAS-CA)
I h (AAS-CA)
I THL
I TLH
Refresh cycle time
RAS high pulse width
RAS low pulse width
CAS low pulse width
CAS high pulse width
CAS hold time after RAS
RAS hold time after CAS
Delay time, CAS to RAS
Delay time, RAS to CAS
Row address setup time before RAS
Column address setup time before CAS
Row address hold time after RAS
Column address hold time after CAS
Column address hold time after RAS
Transition time
(Note 8)
(Noteg)
(Note 10)
Alternative
Symbol
tREF
t RP
t RAS
tCAS
t CPN
ICSH
t RSH
I CRP
, RCD
tASA
IASC
t RAH
t CAH
t AA
tT
--
MH6408AND-15
Limits
Min Max
2
100
150 10000
75 co
35
150
75
-20
30 75
0
0
20
25
95
3 35
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 5
10.
An initial pause of 500ps is required after power·u~ followed by i:lny eight RAS or RAS/CAS cycles before proper device operaTion is achieved.
=The switching characteristics are defined as t THL =t TLH 5ns.
Reference levels of input signals are V 1H min. and VI L max. Reference levels for transition time are also between VI H and VI L.
Except for page· mode.
td{CAS-RAS) requirement IS only applicable for RAS/t:;:AS cycles preceeded by a CAS only cycle (i.e., For systems where CAS has not been decoded with RAS.1
Operation within the td (RAS-CAS) max limit insures that t a (RAS) max can be met. td (RAS- CAS)ma x is specified reference POint only.if
td CRAS-CAS) is greater than the specified td CRAS-CAS) max limit. then access time is controlled exciusivel·1 by ta (CASi
=td (RAS-CAs)mln th (RAS-RA)mln + 2t THL(t TLH) + t su (CA-CAS)mln.
SWITCHING CHARACTERISTICS (Ta=O-70'C, Vcc=5V±10%, VSs=OV, unless~therwisenoted)
Read Cycle
Symbol
teA
Isu (A-CAS)
Ih (cAS-A)
IhiAAS-AI
tdls (CAS)
la (CAS)
ta (AAS)
Parameter
Read cycle time
Read setup time before CAS
Read hold time after CAS
Read hold time after RAS
Output disable time
CAS access time
RAS access time
Alternative
Symbol
(Note II)
(Note 111
INote 12)
(Note 13)
(Note 14)
t AC
t ACS
tACH
tAAH
tOFF
t CAC
I AAC
MH6408AND-15
Limits
Min Max
260
0
0
20
0 40
75
150
Unit
ns
ns
ns
ns
ns
ns
ns
Note 11.
Note 12.
Note 13.
Note 14.
Either th (RAS-R) or th (CAS-R) must be satisfied for a read cycle.
td IS (CAS)maX defines the time at which the outp·ut achieves the open circuit condition and is not reference to VOH or Vo l
= =This is the vauel when td (RAS-CAS) ~ td (RAS-CAs)max. Test conditions; ·Load 2T TL, CL 100pF
This is the value when td (RAS-CAS)< td (RAS-CAs)max. When td (RAS-CAS)~td (RAS-CAS)max. ta (RAS) will increase by the amount that
td (RAS-CAS)eXceeds the value shown. Test conditions; Load = 2T TL, Cl "" 100pF
Write Cycle
Symbol
Parameter
teW
tsu (W-CAS)
th (CAS-W)
th (AAS-W)
th (W-AAS)
th (W-CAS)
tW(W)
Isu (D-CAS)
th (CAS-D)
th (AAS-D)
Wri te cycle time
Write setup time before CAS
Write hold time after CAS
Write hold time after RAS
RAS hold time after write
CAS hold time after write
Writ.e pulse width
Data-in setup time before CAS
Data-in hold time after CAS
Data-in hold time after RAS
Alternative
Symbol
(Note 17)
t AC
twcs
tWCH
'WCA
t AWL
tCWL
twp
t DS
t DH
t DHA
MH6408AND-15
Limits
Min Max
260
-5
45
95
45
45
45
0
45
95
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
• MITSUBISHI
"'ELECTRIC
2-221
5 Page | ||
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| PDF Descargar | [ Datasheet MH6408AND-15.PDF ] | |
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