MH6404AND1-15 Datasheet PDF - Mitsubishi
| Part Number | MH6404AND1-15 | |
| Description | 256K-Bit DRAM | |
| Manufacturers | Mitsubishi | |
| Logo |  |
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MITSUBISHI LSls
MH6404ANDl-15
262 144-BIT (65 536-WORD BY 4-BIT) DYNAMIC RAM
DESCRIPTION
The MH6404AND1 is 65 536-word x 4 bit dynamic RAM
and consists of four industry standard 64K x 1 dynamic
RAMs in leadless chip carrier.
The mounting of leadless chip carriers on a ceramic single
in-line package provides any application where high
densities and large quantities of memory are required.
FEATURES
• High speed
Type name
MH6404ANDl-15
Access time
(max)
Ins}
150
Cycle time
{min}
(ns)
260
Power dissipatio'n
Itypl
ImWI
600
• Utilizes industry standard 64K RAMs in leadless chip
carriers
• 22 pin Single In-line Package
• Single +5V (±1 0%) supply operation
• Low stand by power dissipation ......... 88 mW (max)
• Low operating power dissipation:
MH6404ANDl-15 990mW (max)
• All inputs are directly TTL compatible
• All outputs are three-state and directly TTL compatible
• Includes (0.22J1F x 2) decoupling capacitors
• 128 refresh cycles (every 2ms) A7 Pin is not need for
refresh
PIN CONFIGURATION (TOP VIEW)
NC
15VI
DATA INPUT
Vee
Do
DATA OUTPUT 0 0
~~~g~~I~~B~ESS CA.S
ADDRESS { AA75
INPUTS
A,
DATA INPUT
Dt
DATA OUTPUT
WR ITE CONTROL
INPUT
ADDRESS {
INPUTS
Ot
W
At,
A3
A6
DATA INPUT 0,
DATA OUTPUT D,
ADDRESS
INPUTS
ROW ADDRESS
STROBE INPUT
{ A,
Ao
RAS
DATA INPUT
D3
DATA OUTPUT 03
IOVI Vss
-+
--+
-+
-+
-+
--+
-+
-+
-+
-+
--+
-+
-+
-+
-+
--+
Outline 22S5
D6
~
..~
~
z
0
~
~
..~
~
z
0
~
0
D17
~
~
!
Z
0
"0
APPLICATION
• Main memory unit for computers
• Refresh memory for CRT
BLOCK DIAGRAM
M5K4164AND/AD
64K RAM
M5K4164AND/ AD
64K RAM
M5K4164AND/AD
64K RAM
M5K4164AND/AD
64K RAM
2-196
'MITSUBISHI
.... ELECTRIC
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MITSUBISHI LSls
MH6404ANDl-15
262 144-BIT (6S S36-WORD BY 4-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Page-Mode Cycle)
(Ta =O-70G C Vcc=sv ± 10% VSS=OV unless otherwise noted See notes 5 6 and 7)
Symbol
Parameter
Alternative
Symbol
te AF
t W (RASH)
IW(RASL)
t W(CASL)
I W(CASH)
th(RAS-CAS)
t h(CAS-RAS)
Id (CAS RAS)
Id (RAS-CAS)
I SU(RA-RAS)
t SU(CA-CAS)
t h (RAS-RA)
t" (CAS-CA)
I "(RAS-CA)
t THL
t TLH
Refresh cycle time
RAS high pulse width
RAS low pulse width
CAS low pulse width
CAS high pulse width
(Note 81
CAS hold time after RAS
RAS hold time after CAS
Delay time. CAS to RAS
(Note 91
Oelay time, RAS to CAS
INote 101
Row address setup time before RAS
Column address setup time before CAS
Row address hold time after RAS
Column address hold time after CAS
Column address hold time after RAS
TranSition time
I REF
I RP
I RAS
I CAS
I CPN
I CSH
I RSH
I CRP
I RCD
I ASR
t Ase
t RAH
t CAH
tAR
tT
Min
100
150
75
35
150
75
-20
30
0
0
20
25
95
3
MH6404ANDI-15
Limits
Max
2
1000
00
75
35
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
5
6'
7:
8
10
An initial pause of 50011S is required after power-up followed by any eight RAS or RAS/CAS cycles before proper device operation is achieved
=The switching characteristics are defined as t THL t TLH = 5ns.
Reference levels of Input signals are V,H min and V,L max. Reference levels for transition time are also between V,H and V,L.
Except for page-mode.
td (CAS-RAS) requirement is only applicable for RAS/CAS cycles preceeded by a CAS only cycle (i.e .. For systems where CAS has not been decoded with RAS )
Operation within the td (RAS-CAS) max limit insures that ta (RAS) max can be met. td (RAS-CAS) max IS specified reference point only; if
td (RAS-CAS) IS greater than the specified td eRAS-CAS) max limit, then access time IS controlled exclusively by ta (CAS).
= + +Id(RAS-CAS)mln th (RAS-RA)mln 2t THL( t TLH) tsu (CA-CAS)min-
SWITCHING CHARACTERISTICS (Ta =O-70·C, Vcc~5V±tO%, VSs=OV, unlessotherwlSenoted)
Read Cycle
Symbol
le R
Isu (R-CAS)
Ih (CAS-RI
Ih (RAS-R)
Idis (CAS)
la (CAS)
la (RAS)
Parameter
Read cycle time
Read setup time before CAS
Read hold time after CAS
Read hold time after RAS
Output disable time
CAS access time
RAS access time
Alternative
Symbol
INote 111
INote 111
INote 121
(Note 13)
INote 141
I RC
I RCS
I RCH
I RRH
IOFF
I CAC
I RAC
MH6404ANDl-15
Limits
Min
260
0
0
20
0
Mox
40
75
150
Unit
ns
ns
ns
ns
ns
ns
ns
Note 11'
Note 12
Note 13:
Note 14:
Either th (RAS-A) or th (CAS-R) must be satisfied for a read cycle
tdis(CAS) max defines the time at which the output achieves the open circuit condition and is not reference to VOH or VOL
This is the value when t d ( RAS-CAS) ~ td ( RAS- CAS) max. Test conditions; Load = 2T TL. CL= 100pF
<ThiS IS the value when td (RAS-CAS) td (RAS-CAS) max. When td (RAS-CAS) ~ td (RAS-CAS) max, ta (RAS) will increase by the amount that
td (RAS-CAS) exceeds the value shown. Test conditions; load = 2T TL, CL= 100pF
Write Cycle
Symbol
Parameter
lew
tsu (W-CAS)
Ih (CAS-WI
Ih (RAS-W)
Ih (W-RAS)
Ih (W-CAS)
Iw(w)
ISll CD-CAS)
Ih (CAS-D)
Ih (RAS-O)
Wrrte cycle time
Wrrte setup time before CAS
Write hold time after CAS
Write hold time after RAS
RAS hold time after wrrte
CAS hold time after write
Write pulse width
Data-In setup time before CAS
Data-In hold time after CAS
Data ·In hold time after RAS
Alternative
Symbol
(Note 171
I RC
I wcs
IWCH
IWCR
I RWL
ICWL
Iwp
los
IOH
IOHR
Min
260
-5
45
95
45
45
45
0
45
95
MH6404ANDl-15
Limits
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IiY'.&
MITSUBISHI
ELECTRIC
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