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PDF MH6404AD1-15 Data sheet ( Hoja de datos )
| Número de pieza | MH6404AD1-15 | |
| Descripción | 256K-Bit DRAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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MITSUBISHI LSls
MH6404AD1·15
262 144-BIT (6S S36-WORD BY 4-BIT) DYNAMIC RAM
DESCRIPTION
The MH6404AD1 is 65 536-word x 4 bit dynamic RAM and
consists of four industry standard 64 K x 1 dynamic RAMs
in leadless chip carrier.
The mounting of leadless chip carriers on a ceramic
single in-line package provides any application where high
densities and large quantities of memory are required.
FEATURES
• High speed
Type name
MH6404ADI-15
Access time
(max)
(ns)
150
Cycle time
(min)
Insl
260
Power dissipation
ltypl
ImWI
600
• Utilizes industry standard 64K RAMs in leadless chip
carriers
• 22 pin Single In-line Package
• Single +5V (±1 0%) supply operation
• Low stand by power dissipation ........ 88 mW(max)
• Low operating power dissipation:
MH6404ADl-15 990mW(max)
• All inputs are directly TTL compatible
• All outputs are three-state and directly TTL compatible
• Includes (0.22,uF x 2) decoupling capacitors
• 128 refresh cycles (every 2ms) A7 Pin is not need for
refresh
• Pin 1 controls automatic-and self-refresh mode
PIN CONFIGURATION (TOP VIEW)
REFRESH
INPUT
15V)
DATA INPUT
REF
Vee
Do
DATA OUTPUT 0 0
CDLUMN ADDRESS
STROBE INPUT
CAS
AJ
ADDRESS { As
INPUTS
A,
DATA INPUT
01
DATA OUTPUT
WRITE CONTROL
INPUT
ADDRESS {
INPUTS
01
W
Al
A3
A6
DATA INPUT
0,
DATA OUTPUT 0,
{ADDRESS
INPUTS
A,
Ao
ROW ADDRESS
STROBE INPUT
RAS
DATA INPUT
03
DATA OUTPUT 03
IOV) Vss
-+
--+
-+
-+
-+
--+
-+
-+
-+
--+
-+
-+
-+
-+
--+
-+
II]4 »
0
5
G6
II], ~
, :.>..;.
~10
11
II]~13
~
14
15
.C»..;.;
0
16
G17
lU~19
20 ::
a>
21 ; :
22 0
Outline 2255
APPLICATION
• Main memory unit for computers
• Refresh memory for CRT
BLOCK DIAGRAM
Do 00
M5K4164AD
64K RAM
M5K4164AD
64K RAM
M5K4164AD
64K RAM
M5K4164AD
64K RAM
• MITSUBISHI
"ELECTRIC
I
----JJ-I
Vee Vss
2-185
1 page  
MITSUBISHI LSls
MH6404AD1·15
262 144-BIT (65 536-WORD BY 4.BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Page-Mode Cycle)
(Ta=O~70°C. Vcc=5V±10%. Vss=OV, unless otherwise noted, See notes 5,6 and 7)
Symbol
Parameter
Alternative
Symbol
teRF
t IN (RASH)
t W(RASLI
t IN (CASU
t W (CASH)
th(RAS-CAS)
t h (CAS- RAS)
td (CAS RAS)
td (RAS-CAS)
t SU(RA-RAS)
t su (CA-CAS)
t h (RAS-RA)
t h (CAS-CA)
t h (RAS-CA)
t THL
t TLH
Refresh cycle time
RAS high pulse width
RAS low pulse width
CAS low pulse width
CAS high pulse width
CAS hold time after RAS
INote 81
RAS hold time after CAS
Delay time, CAS to RAS
Delay time, RAS to CAS
INote 91
INote 101
Row address setup time before RAS
Column address setup time before CAS
Row address hold time aher RAS
Column address hold time after CAS
Column address hold timp. after RAS
Transition time
I REF
I RP
I RAS
ICAS
I CPN
I CSH
I RSH
I CRP
I RCO
I ASR
lASe
I RAH
I CAH
I AR
IT
MH6404ADI-15
Limits
Min
100
150
75
35
150
75
-20
30
a
a
20
25
95
3
Max
2
10000
00
75
35
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
9:
10:
An initial pause of 500,us is required after power-up followed by any eight RAS or RAS/CAS cycles before proper deVice operation is achieved
= =The switching characteristics are defined as t THL t TLH Sns.
Reference levels of input signals are VIHmin and VILmax. Reference levels for transition time are also between VIH and VIL.
Except for page-mode
td (CAS-RAS) requirement is only applicable for RAS/CAS cycles preceeded by a CAS only cycle {i.e .. For systems where CAS has not been decoded with RAS )
Operation within the td (RAS-CAS) max limit insures that ta (RAs)maX can be met. td (RAS-CAS) max ·IS specified reference point only;if
td (RAS-CAS) IS greater than the specified td (RAS"CAS) max limit, then access time IS controlled exclusively by ta (CAS).
+ +td(RAS-CAS)min = Ih (RAS-RA)min 2t THL( tTLH) Isu (CA-CAS)min-
SWITCHING CHARACTERISTICS (Ta =O-70'C, Vec=5V ± 10%. VSS=OV. unless otherwISe noted)
Read Cycle
Symbol
teR
Isu (R-CAS)
Ih (CAS-R)
Ih (RAS-R)
tdls (CAS)
la (CAS)
ta (RAS)
Parameter
Read cycle time
Read setup time before CAS
Read hold time after CAS
Read hold time after RAS
Output disable time
-
CAS access time
RAS access time
Alternative
Symbol
INote 111
INote 111
INote 121
(Note 131
INote 14)
I RC
I RCS
I RCH
I RRH
IOFF
tCAC
tRAC
MH6404ADl-15
Limits
Min
260
a
a
20
a
Max
40
75
150
Unit
ns
ns
ns
ns
ns
ns
ns
Note 11:
Note 12:
Note 13:
Note 14"
Either th (RAS-R) or th (CAS-R) must be satisfied for a read cycle
tdis(CAS) max defines the time at which the output achieves the open circuit condition and is not reference to VOH or VOL
This is the value when td (RAS-CAS) ~ td (RAS-CAS) max. Test conditions; Load=2T TL. CL= 100pF
<This is the value when td (RAS-CAS) td (RAS-CAS) max. When td (RAS-CAS) ~ td (RAS-CAS) max, ta (RAS) will increase by the amount that
td (RAS-CAS) exceeds the value shown Test conditions;-Load=2T TL. CL=100pF
Write Cycle
Symbol
Parameter
tew
Isu IW-CAS)
Ih (CAS-W)
Ih (RAS-W)
Ih (W-RASI
th (W-CAS)
Iw(w)
Isu (O-CAS)
th (CAS-D)
th (RAS-O)
Write cycle time
Write setup time before CAS
Write hold time after CAS
Write hold time after RAS
RAS hold time after write
CAS hold time after write
Wnte pulse width
Data-in setup time before CAS
Data-in hold time after CAS
Data·in hold time after RAS
Alternative
Symbol
INote 171
IRC
twcs
tWCH
tWCR
tRWL
tCWL
twp
t OS
tOH
t DHR
MH6404ADl-15
Limits
Min
260
5
45
95
45
45
45
a
45
95
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
• .MITSUBISHI
.... ELECTRIC
2-189
5 Page 
MITSUBISHI LSI.
MH6404AD1·15
262 144·BIT (65 536·WORD BY 4.BIT) DYNAMIC RAM
Hidden Self-Refresh Cycle INote 22)
READ CYCLE
W V,H
V,L
REF
V,H
V,L
VOH
Q
VOL
DATA VALID
Note 22: If the pin 1 (REF) function is not used, pin 1 rnay be left open (not connect).
Hidden Refresh Cycle INote 19)
READ CYCLE
teR
REFRESH CYCLE
teR
t w ( RASL)
tW(RASL)
td(CAS-RAS)
td (RAS-CAS)
tw (RASH)
th(CAS-RAS)
tW(CASL)
tdls (CAS)
REFRESH CYCLE
tOR
tW(RASL)
tw (RASH)
twICASH)
tsueRA-RAS) th(RAS-RA)
tsu (RA- RAS)
V,H
W
V,L
VOH
Q
VOL
DATA VALID
• MITSUBISHI
..... ELECTRIC
tdls (CAS)
2-195
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet MH6404AD1-15.PDF ] | |
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