PDF ADAU1777 Data sheet ( Hoja de datos )

Número de pieza	ADAU1777
Descripción	Low Power Codec
Fabricantes	Analog Devices
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Data Sheet Four-ADC, Two-DAC, Low Power Codec with Audio Processor ADAU1777 FEATURES APPLICATIONS Programmable audio processing engine Noise canceling handsets, headsets, and headphones Fast (up to 768 kHz) and slow processing paths Bluetooth® active noise canceling (ANC) handsets, headsets, Biquad filters, limiters, volume controls, and mixing and headphones Low latency, 24-bit ADCs and DACs Personal navigation devices 102 dB SNR (through PGA and ADC with A weighted filter) Digital still and video cameras 108 dB combined SNR (through DAC and headphone with A weighted filter) Serial port sampling rate from 8 kHz to 192 kHz 5 μs analog-to-analog latency 4 single-ended analog inputs, configurable as microphone or line inputs Dual stereo digital microphone inputs Stereo analog audio output, single-ended or differential, configurable as either line output or headphone driver PLL supporting any input clock rate from 8 MHz to 27 MHz GENERAL DESCRIPTION The ADAU1777 is a codec with four inputs and two outputs that incorporates a digital processing engine to perform filtering, level control, signal level monitoring, and mixing. The path from the analog input to the DSP core to the analog output is optimized for low latency and is ideal for noise canceling headsets. With the addition of just a few passive components, a crystal, and an EEPROM for booting, the ADAU1777 provides a complete headset solution. Full duplex, asynchronous sample rate converters (ASRCs) Power supplies Analog and digital input/output of 1.8 V to 3.3 V Digital signal processing (DSP) core of 1.1 V to 1.8 V Low power Note that throughout this data sheet, multifunction pins, such as SCL/SCLK, are referred to either by the entire pin name or by a single function of the pin, for example, SCLK, when only that function is relevant. I2C and SPI control interfaces, self boot from I2C EEPROM 7 multipurpose (MPx) pins for digital controls and outputs FUNCTIONAL BLOCK DIAGRAM MICBIAS0 MICBIAS1 AIN0 AIN1 DMIC0_1/MP4 DMIC2_3/MP5 AIN2 AIN3 CM MICROPHONE BIAS GENERATORS PGA ADC PGA ADC DIGITAL MICROPHONE INPUTS PGA ADC PGA ADC POWER MANAGEMENT LDO REGULATOR ADAU1777 PLL CLOCK OSCILLATOR INPUT/OUTPUT SIGNAL ROUTING DSP CORE: BIQUAD FILTERS, LIMITERS, VOLUME CONTROLS, MIXING DAC STEREO PDM MODULATOR DAC BIDIRECTIONAL ASRCS SERIAL INPUT/ OUTPUT PORT I2C/SPI CONTROL INTERFACE AND SELF BOOT ADC_SDATA1/CLKOUT/MP6 XTALI/MCLKIN XTALO HPOUTLP/LOUTLP HPOUTLN/LOUTLN HPOUTRP/LOUTRP HPOUTRN/LOUTRN DAC_SDATA/MP0 ADC_SDATA0/PDMOUT/MP1 BCLK/MP2 LRCLK/MP3 Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page ADAU1777 Data Sheet SPECIFICATIONS Master clock = 12.288 MHz, serial input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word width = 24 bits, TA = 25°C, outputs line loaded with 10 kΩ. ANALOG PERFORMANCE SPECIFICATIONS AVDD = IOVDD = 1.8 V, DVDD = 1.1 V, unless otherwise noted. Phase-locked loop (PLL) disabled, direct master clock. Table 1. Parameter ANALOG-TO-DIGITAL CONVERTERS (ADCs) ADC Resolution Digital Attenuation Step Digital Attenuation Range INPUT RESISTANCE Single-Ended Line Input Programmable Gain Amplifier (PGA) Inputs LINE INPUT Full-Scale Input Voltage Dynamic Range1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Signal-to-Noise Ratio (SNR)2 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Interchannel Gain Mismatch Total Harmonic Distortion + Noise (THD + N) Offset Error Gain Error Interchannel Isolation Power Supply Rejection Ratio (PSRR) PGA INPUT Full-Scale Input Voltage Dynamic Range1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Test Conditions/Comments All ADCs Gain settings do not include 10 dB gain from PGA_x_BOOST settings; this additional gain does not affect input impedance; PGA_POP_DISx = 1 0 dB gain −12 dB gain 0 dB gain +35.25 dB gain PGA_ENx = 0, PGA_x_BOOST = 0, PGA_POP_DISx = 1 Scales linearly with AVDD AVDD = 1.8 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 3.3 V 20 Hz to 20 kHz, −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V 20 Hz to 20 kHz, −1 dB from full-scale input AVDD = 1.8 V AVDD = 3.3 V CM capacitor = 22 μF CM capacitor = 22 μF, 100 mV p-p at 1 kHz PGA_ENx = 1, PGA_x_BOOST = 0 Scales linearly with AVDD AVDD = 1.8 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 3.3 V 20 Hz to 20 kHz, −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V Min 95 99 92 96 96 100 92 96 0 −0.11 −0.4 Typ 24 0.375 95 Max Unit Bits dB dB 14.3 kΩ 32.0 kΩ 20 kΩ 0.68 kΩ AVDD/3.3 0.55 1.54 1.00 2.83 V rms V rms V p-p V rms V p-p 97 dB 102 dB 94 dB 99 dB 98 dB 103 dB 96 dB 100 dB 40 200 mdB −90 −83 dB −94 −87 dB +0.12 mV +0.2 dB 95 dB 55 dB AVDD/3.3 0.55 1.54 1.00 2.83 V rms V rms V p-p V rms V p-p 94 dB 102 dB 92 dB 98 dB Rev. 0 \| Page 4 of 108 5 Page ADAU1777 Data Sheet DIGITAL TIMING SPECIFICATIONS −40°C < TA < +85°C, IOVDD = 1.71 V to 3.63 V, DVDD = 1.045 V to 1.98 V. Table 7. Digital Timing Parameter MASTER CLOCK (MCLK) tMP tMCLK SERIAL PORT tBL tBH tLS tLH tSS tSH tTS tSOD tSOTD tSOTX SERIRAL PERIPHERAL INTERFACE (SPI) PORT fSCLK tCCPL tCCPH tCLS tCLH tCLPH tCDS tCDH tCOD I2C PORT fSCL tSCLH tSCLL tSCS tSCR tSCH tDS tSCF tBFT I2C EEPROM SELF BOOT tSCHE tSCSE tBFTE tDSE tBHTE Limit tMIN tMAX 37 125 77 82 40 40 10 10 5 5 10 0 34 30 30 6.25 80 80 5 100 80 10 10 101 400 0.6 1.3 0.6 250 0.6 100 250 0.6 26 × tMP − 70 38 × tMP − 70 70 × tMP − 70 6 × tMP − 70 32 × tMP Unit Description ns MCLKIN period; 8 MHz to 27 MHz input clock using PLL ns Internal MCLK period; direct MCLK and PLL output divided by 2 ns BCLK low pulse width (master and slave modes) ns BCLK high pulse width (master and slave modes) ns LRCLK setup; time to BCLK rising (slave mode) ns LRCLK hold; time from BCLK rising (slave mode) ns DAC_SDATA setup; time to BCLK rising (master and slave modes) ns DAC_SDATA hold; time from BCLK rising (master and slave modes) ns BCLK falling to LRCLK timing skew (master mode) ns ADC_SDATAx delay; time from BCLK falling (master and slave modes) ns BCLK falling to ADC_SDATAx driven in time-division multiplexing (TDM) tristate mode ns BCLK falling to ADC_SDATAx tristate in TDM tristate mode MHz SCLK frequency ns SCLK pulse width low ns SCLK pulse width high ns SS setup; time to SCLK rising ns SS hold; time from SCLK rising ns SS pulse width high ns MOSI setup; time to SCLK rising ns MOSI hold; time from SCLK rising ns MISO delay; time from SCLK falling kHz SCL frequency µs SCL high µs SCL low µs SCL rise setup time (to SDA falling), relevant for repeated start condition ns SCL and SDA rise time, CLOAD = 400 pF µs SCL fall hold time (from SDA falling), relevant for start condition ns SDA setup time (to SCL rising) ns SCL and SDA fall time; CLOAD = 400 pF µs SCL rise setup time (to SDA rising), relevant for stop condition ns SCL fall hold time (from SDA falling), relevant for start condition; tMP is the input clock on the MCLKIN pin ns SCL rise setup time (to SDA falling), relevant for repeated start condition ns SCL rise setup time (to SDA rising), relevant for stop condition ns Delay from SCL falling to SDA changing ns SDA rising in self boot stop condition to SDA falling edge for external master start condition Rev. 0 \| Page 10 of 108 11 Page

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