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M5M29FT800VP-12 Datasheet PDF


8M-Bit BLOCK ERASE FLASH MEMORY - Mitsubishi

Part Number M5M29FT800VP-12
Description 8M-Bit BLOCK ERASE FLASH MEMORY
Manufacturers Mitsubishi 
Logo Mitsubishi Logo 
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M5M29FT800VP-12 datasheet
---------------------------------------------
M5M29FT800VP-12 pdf, equivalent, schematic
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
BLOCK DIAGRAM
ADDRESS
INPUTS
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CHIP ENABLE INPUT
OUTPUT ENABLE INPUT
WRITE ENABLE INPUT
WRITE PROTECT INPUT
RESET/POWER DOWN INPUT
BYTE ENABLE INPUT
/CE
/OE
/WE
/WP
/RP
/BYTE
READY/BUSY OUTPUT RY/BY
X-DECODER
128 WORD PAGE BUFFER
Boot Block
Parameter Block1
Parameter Block2
Main Block
8KW
4KW
4KW
16KW
Main Block
32KW
VCC (3.3V)
GND (0V)
Y-DECODER
Main Block
32KW
Y-GATE / SENSE AMP.
STATUS / ID REGISTER
CUI WSM
MULTIPLEXER
INPUT/OUTPUT
BUFFERS
D15/A-1D14D13 D12
D3 D2 D1 D0
DATA INPUTS/OUTPUTS
FUNCTION
The M5M29FB/T800FP,VP,RV includes on-chip program/erase
control circuitry. The Write State Machine (WSM) controls block
erase and page program operations. Operational modes are
selected by the commands written to the Command User Interface
(CUI). The Status Register indicates the status of the WSM and
when the WSM successfully completes the desired program or
block erase operation.
A Deep Powerdown mode is enabled when the /RP pin is at GND,
minimizing power consumption.
Read
The M5M29FB/T800FP,VP,RV has three read modes, which
accesses to the memory array, the Device Identifier and the Status
Register. The appropriate read command are required to be
written to the CUI. Upon initial device powerup or after exit from
deep powerdown, the M5M29FB/T800 automatically resets to read
array mode. In the read array mode, low level input to /CE and
/OE, high level input to /WE and /RP, and address signals to the
address inputs (A0-A18) output the data of the addressed location
to the data input/output(D0-15).
Write
Writes to the CUI enables reading of memory array data, device
identifiers and reading and clearing of the Status Register. They
also enable block erase and program. The CUI is written by
bringing /WE to low level, while /CE is at low level and /OE is at
high level. Address and data are latched on the earlier rising edge
of /WE and /CE. Standard micro-processor write timings are used.
Output Disable
When /OE is at VIH, output from the devices is disabled.
Data input/output are in a high-impedance(High-Z) state.
Standby
When /CE is at VIH, the device is in the standby mode and its
power consumption is reduced. Data input/output are in a
high-impedance(High-Z) state. If the memory is deselected during
block erase or program, the internal control circuits remain active
and the device consume normal active power until the operation
completes.
Deep Power-Down
When /RP is at VIL, the device is in the deep powerdown
mode and its power consumption is substantially low. During
read modes, the memory is deselected and the data
input/output are in a high-impedance(High-Z) state. After
return from powerdown, the CUI is reset to Read Array , and
the Status Register is cleared to value 80H.
During block erase or program modes, /RP low will abort
either operation. Memory array data of the block being altered
become invalid.
2 May 1997 , Rev.6.1
---------------------------------------------
M5M29FT800VP-12 transistor, diode fet, igbt, scr
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Vcc POWER UP / DOWN TIMING
3.3V
VCC
GND
/RP VIH
VIL
Read /Write Inhibit
tVCS
/CE VIH
VIL
tPS
/WE
VIH
VIL
Read /Write Inhibit
tPS
Read /Write Inhibit
AC WAVEFORMS FOR READ OPERATION AND TEST CONDITIONS
VIH
ADDRESSES
VIL
VIH
/CE
VIL
/OE VIH
VIL
/WE
DATA
VIH
VIL
VOH
VOL
/RP VIH
VIL
HIGH-Z
tPS
ADDRESS VALID
tRC
ta (AD)
ta (CE)
tDF(CE)
tOEH
tCLZ
ta (OE)
tOLZ
tDF(OE)
tOH
OUTPUT VALID
tPHZ
HIGH-Z
TEST CONDITIONS
FOR AC CHARACTERISTICS
Input voltage : VIL = 0V, VIH = 3.0V
Input rise and fall times : 5ns (80ns)
10ns (100/120ns)
Reference voltage
at timing measurement : 1.5V
Output load : 1TTL gate +
CL(100pF for 100/120ns)
CL(30pF for 80ns)
or
1.3V
1N914
3.3k
DUT
CL =30/100pF
BYTE AC WAVEFORMS FOR READ OPERATION
ADDRESSES VIH
(A0 - A18) VIL
VIH
/CE
VIL
VIH
/OE
VIL
/BYTE
VIH
VIL
VIH
DATA
(D0 - D7) VIL
HIGH-Z
ADDRESS VALID
ta(AD)
ta(CE)
ta(OE)
ta(BYTE)
tOLZ
tCLZ
tBAD
tBCD
tBAD
OUTPUT VALID
DATA
VIH
(D8 - D14) VIL
HIGH-Z
ADDRESS VALID
ta(BYTE)
VALID
tBHZ
VALID
VALID
ta(AD)
tDF(CE)
tDF(OE)
tOH
D15 / A-1 VIH
VIL
A-1 D15 A-1
When /BYTE=VIH, /CE=/OE=VIL , D15/A-1 is output status. At this time, input signal must not be applied.
9
May 1997 , Rev.6.1





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