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M5M29FB800VP-12 PDF Datasheet - 8M-Bit BLOCK ERASE FLASH MEMORY - Mitsubishi

Part Number M5M29FB800VP-12
Description 8M-Bit BLOCK ERASE FLASH MEMORY
Manufacturers Mitsubishi 
Logo Mitsubishi Logo 
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M5M29FB800VP-12 datasheet, circuit
MITMSIUTSBUISBHISI HLISILsSIs
M5M29FBM/T58M0290FFBP/T,8V00PF,PR,VVP-,8R0V-,8-01,0-1,0-,1-122
8,388,388,680,680-B8-IBT I(T10(14084,587,567-W6-OWRODRDBYB8Y-B8-IBT I/T5/2542,248,288-W8-OWRODRDBYB1Y61-B6-IBT)IT)
CMCOMSO3S.33V.3-OVN-OLNYL, YB, LBOLCOKCEKREARSAESFELFALSAHSMHEMMEOMROYRY
DESCRIPTION
The MITSUBISHI M5M29FB/T800FP, VP, RV are 3.3V-only high speed 8,388,608-bit CMOS boot block Flash Memories suitable for
mobile and personal computing, and communication products. The M5M29FB/T800FP, VP, RV are fabricated by CMOS technology for
the peripheral circuits and DINOR(Divided bit line NOR) architecture for the memory cells, and are available in 44pin SOP or 48pin
TSOP(I).
FEATURES
Organization
................................. 524,288 word x 16bit
................................. 1,048,576 word x 8 bit
Supply voltage ............................................................. VCC = 3.3V±0.3V
Access time
.............................. 80/100/120ns (Max)
PIN CONFIGURATION (TOP VIEW)
Power Dissipation
Read
....................... 108 mW (Max.)
Program/Erase
....................... 144 mW (Max.)
Standby
....................... 0.72 mW (Max.)
Deep power down mode ....................... 3.3µW (typ.)
Auto program
Program Time
....................... 7.5ms (typ.)
Program Unit ................................. 128word
Auto Erase
Erase time
................................. 50 ms (typ.)
Erase Unit
Boot Block ................................. 8Kword / 16Kbyte x 1
Parameter Block ........................ 4Kword / 8Kbyte x 2
Main Block
.......................16Kword / 32Kbyte x 1
........................... 32Kword / 64Kbyte x 15
Program/Erase cycles ....................................... 100Kcycles
NC
A18
A17
A7
A6
ADDRESS
INPUTS
A5
A4
A3
A2
A1
CHIP ENABLE
INPUT
A0
/CE
GND
OUTPUT ENABLE
INPUT
/OE
DQ0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RESET/
44
/RP
POWER DOWN
INPUT
43 /WE WRITE ENABLE
INPUT
42 A8
41 A9
40 A10
39 A11
ADDRESS
38 A12 INPUTS
37 A13
36 A14
35 A15
34 A16
33
/BYTE
BYTE ENABLE
INPUT
32 GND
31 DQ15/A-1
30 DQ7
Boot Block
M5M29FB800
M5M29FT800
Other Functions
........................... Bottom Boot
........................... Top Boot
DATA
INPUTS/
OUTPUTS
DQ8
DQ1
DQ9
DQ2
16
17
18
19
29 DQ14
28 DQ6
27 DQ13
26 DQ5
DATA
INPUTS/
OUTPUTS
Software Command Control
DQ10 20
25 DQ12
Selective Block Lock
Erase Suspend/Resume
Program Suspend/Resume
DQ3
DQ11
21
22
24 DQ4
23 VCC
Status Register Read
Sleep
Package
Outline 600mil 44-pin SOP
(FP: 44P2A-A)
48-Lead, 12mmx 20mm TSOP (type-I)
44-Lead SOP
APPLICATION
Code Storage PC BIOS
Digital Cellular Phone/Telecommunication
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
/WE
/RP
NC
/WP
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
M5M29FB/T800VP
48 A16
47 /BYTE
A16
/BYTE
1
2
46 GND
GND
3
45 DQ15/A-1 DQ15/A-1
4
44 DQ7
43 DQ14
DQ7
DQ14
5
6
42 DQ6
DQ6
7
41 DQ13
40 DQ5
DQ13
DQ5
8
9
39 DQ12
DQ12
10
38 DQ4
37 VCC
36 DQ11
35 DQ3
DQ4
VCC
DQ11
DQ3
11
12
13
14
34 DQ10
33 DQ2
DQ10
DQ2
15
16
32 DQ9
31 DQ1
30 DQ8
DQ9
DQ1
DQ8
17
18
19
29 DQ0
28 /OE
DQ0
/OE
20
21
27 GND
26 /CE
GND
/CE
22
23
25 A0
A0 24
M5M29FB/T800RV
48 A15
47 A14
46 A13
45 A12
44 A11
43 A10
42 A9
41 A8
40 NC
39 NC
38 /WE
37 /RP
36 NC
35 /WP
34 RY/BY
33 A18
32 A17
31 A7
30 A6
29 A5
28 A4
27 A3
26 A2
25 A1
Outline 48pin TSOP type-I (12 X 20mm)
VP(Normal bend): 48P3R-B
RV(Reverse bend): 48P3R-C
NC : NO CONNECTION
This product is compatible with HN29WB/T800 by Hitachi Ltd.
1 May 1997 , Rev.6.1

1 page

M5M29FB800VP-12 pdf, schematic
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
BLOCK DIAGRAM
ADDRESS
INPUTS
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CHIP ENABLE INPUT
OUTPUT ENABLE INPUT
WRITE ENABLE INPUT
WRITE PROTECT INPUT
RESET/POWER DOWN INPUT
BYTE ENABLE INPUT
/CE
/OE
/WE
/WP
/RP
/BYTE
READY/BUSY OUTPUT RY/BY
X-DECODER
128 WORD PAGE BUFFER
Boot Block
Parameter Block1
Parameter Block2
Main Block
8KW
4KW
4KW
16KW
Main Block
32KW
VCC (3.3V)
GND (0V)
Y-DECODER
Main Block
32KW
Y-GATE / SENSE AMP.
STATUS / ID REGISTER
CUI WSM
MULTIPLEXER
INPUT/OUTPUT
BUFFERS
D15/A-1D14D13 D12
D3 D2 D1 D0
DATA INPUTS/OUTPUTS
FUNCTION
The M5M29FB/T800FP,VP,RV includes on-chip program/erase
control circuitry. The Write State Machine (WSM) controls block
erase and page program operations. Operational modes are
selected by the commands written to the Command User Interface
(CUI). The Status Register indicates the status of the WSM and
when the WSM successfully completes the desired program or
block erase operation.
A Deep Powerdown mode is enabled when the /RP pin is at GND,
minimizing power consumption.
Read
The M5M29FB/T800FP,VP,RV has three read modes, which
accesses to the memory array, the Device Identifier and the Status
Register. The appropriate read command are required to be
written to the CUI. Upon initial device powerup or after exit from
deep powerdown, the M5M29FB/T800 automatically resets to read
array mode. In the read array mode, low level input to /CE and
/OE, high level input to /WE and /RP, and address signals to the
address inputs (A0-A18) output the data of the addressed location
to the data input/output(D0-15).
Write
Writes to the CUI enables reading of memory array data, device
identifiers and reading and clearing of the Status Register. They
also enable block erase and program. The CUI is written by
bringing /WE to low level, while /CE is at low level and /OE is at
high level. Address and data are latched on the earlier rising edge
of /WE and /CE. Standard micro-processor write timings are used.
Output Disable
When /OE is at VIH, output from the devices is disabled.
Data input/output are in a high-impedance(High-Z) state.
Standby
When /CE is at VIH, the device is in the standby mode and its
power consumption is reduced. Data input/output are in a
high-impedance(High-Z) state. If the memory is deselected during
block erase or program, the internal control circuits remain active
and the device consume normal active power until the operation
completes.
Deep Power-Down
When /RP is at VIL, the device is in the deep powerdown
mode and its power consumption is substantially low. During
read modes, the memory is deselected and the data
input/output are in a high-impedance(High-Z) state. After
return from powerdown, the CUI is reset to Read Array , and
the Status Register is cleared to value 80H.
During block erase or program modes, /RP low will abort
either operation. Memory array data of the block being altered
become invalid.
2 May 1997 , Rev.6.1

2 Page

M5M29FB800VP-12 equivalent
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
SOFTWARE COMMAND DEFINITION
Command List
1st bus cycle
2nd bus cycle
3rd bus cycle
Command
Mode Address Data
(D7-0)
Mode
Address
Data
(D7-0)
Mode
Address
Data
(D7-0)
Read Array
Device Identifier
Read Status Register
Clear Status Register
Page Program 4)
Block Erase / Confirm
Suspend
Resume
Read Lock Bit Status
Lock Bit Program / Confirm
Erase All Unlocked Blocks
Sleep 7)
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
X FFH
X
90H Read
IA 2)
ID 2)
X 70H Read
X SRD3)
X 50H
X
41H Write
WA0 4) WD0 4) Write
WA1
WD1
X
20H Write
BA 5)
D0H
X B0H
X D0H
X
71H Read
BA
DQ6 6)
X
77H Write
BA
D0H
X A7H Write X D0H
X F0H
1) In the word-wide mode, upper byte data (D8-D15) is ignored.
2) IA=ID Code Address : A0=VIL (Manufacturer's Code) : A0=VIH (Device Code), ID=ID Code,
/BYTE =VIL : A-1, A1-A18 = VIL, /BYTE =VIH : A1-A18 = VIL
3) SRD = Status Register Data
4) WA=Write Address, WD=Write Data.
/BYTE =VIL : Write Address and Write Data must be provided sequentially from 00H to FFH for A-1-A6.
Page size is 256Byte (256byte x 8bit), /BYTE =VIH : Write Address and Write Data must be provided
sequentially from 00H to 7FH for A0-A6. Page size is 128word (128word x 16bit).
5) BA = Block Address ( Addresses except Block Address mest be VIH.)
6) DQ6 provides Block Lock Status, DQ6 = 1 : Block Unlock, DQ6 = 0 : Block Locked.
7) Sleep command (F0H) put the device into the sleep mode after completing the current operation. The active current is reduced to deep power -down levels.
The Read Array command (FFH) must be written to get the device out of sleep mode.
BLOCK LOCKING
SOP Package
/RP Lock Bit(Internally)
/RP
TSOP Package
/WP Lock Bit(Internally)
Write Protection Provided
VIL X
VIL X
X
All Blocks Locked (Deep Power Down Mode)
VHH
X
VHH
X
X
All Blocks UnLocked
VIH 0
VIH 1
VIH VIL
VIH VIL
0
1
Blocks Locked (Depend on Lock Bit Data)
Blocks Unlocked (Depend on Lock Bit Data)
VIH VIH
X
All Blocks Unlocked
D6 provides Lock Status of each block after writing the Read Lock Status command (71H).
In case of TSOP package, /WP pin must not be switched during performing Read / Write operations or WSM Busy (WSMS = 0).
STATUS REGISTER
Symbol
SR.7
SR.6
SR.5
SR.4
SR.3
SR.2
SR.1
SR.0
(D7)
(D6)
(D5)
(D4)
(D3)
(D2)
(D1)
(D0)
Status
Write State Machine Status
Suspend Status
Erase Status
Program Status
Block Status after Program
Reserved
Reserved
Device Sleep Status
"1"
Ready
Suspended
Error
Error
Error
-
-
Device in Sleep
Definition
"0"
Busy
Operation in Progress / Completed
Successful
Successful
Successful
-
-
Device Not in Sleep
*The RY/BY is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation.
A pull-up resistor of 10K-100K Ohms is required to allow the RY/BY signal to transition high indicating a Ready WSM condition.
*D3 indicates the block status after the page programming. When D3 is "1", the page has the over-programed cell . If over-program occures, the device is block
fail. However if D3 is "1", please try the block erase to the block. The block may revive.
DEVICE IDENTIFIER CODE
Code
Pins
A0
D7 D6 D5 D4 D3 D2 D1 D0 Hex. Data
Manufacturer Code
VIL
0 00111 00
1CH
Device Code (-T)
VIH
010
1 1 10
1
5DH
Device Code (-B)
VIH
010 11 110
5EH
In the word-wide mode, the same data as D7-0 is read out from D15-8.
A9 = VHH Mode : A9 = 11.5V~13.0V Set A9 to VHH min.200ns before falling edge of /CE in ready status. Min.200ns after return to VIH ,device can't be accessed.
A1~A8, A10~A18, /CE,/OE = VIL, /WE = VIH
D15/A-1 = VIL (/BYTE = L)
5 May 1997 , Rev.6.1

5 Page

M5M29FB800VP-12 diode, scr
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Vcc POWER UP / DOWN TIMING
3.3V
VCC
GND
/RP VIH
VIL
Read /Write Inhibit
tVCS
/CE VIH
VIL
tPS
/WE
VIH
VIL
Read /Write Inhibit
tPS
Read /Write Inhibit
AC WAVEFORMS FOR READ OPERATION AND TEST CONDITIONS
VIH
ADDRESSES
VIL
VIH
/CE
VIL
/OE VIH
VIL
/WE
DATA
VIH
VIL
VOH
VOL
/RP VIH
VIL
HIGH-Z
tPS
ADDRESS VALID
tRC
ta (AD)
ta (CE)
tDF(CE)
tOEH
tCLZ
ta (OE)
tOLZ
tDF(OE)
tOH
OUTPUT VALID
tPHZ
HIGH-Z
TEST CONDITIONS
FOR AC CHARACTERISTICS
Input voltage : VIL = 0V, VIH = 3.0V
Input rise and fall times : 5ns (80ns)
10ns (100/120ns)
Reference voltage
at timing measurement : 1.5V
Output load : 1TTL gate +
CL(100pF for 100/120ns)
CL(30pF for 80ns)
or
1.3V
1N914
3.3k
DUT
CL =30/100pF
BYTE AC WAVEFORMS FOR READ OPERATION
ADDRESSES VIH
(A0 - A18) VIL
VIH
/CE
VIL
VIH
/OE
VIL
/BYTE
VIH
VIL
VIH
DATA
(D0 - D7) VIL
HIGH-Z
ADDRESS VALID
ta(AD)
ta(CE)
ta(OE)
ta(BYTE)
tOLZ
tCLZ
tBAD
tBCD
tBAD
OUTPUT VALID
DATA
VIH
(D8 - D14) VIL
HIGH-Z
ADDRESS VALID
ta(BYTE)
VALID
tBHZ
VALID
VALID
ta(AD)
tDF(CE)
tDF(OE)
tOH
D15 / A-1 VIH
VIL
A-1 D15 A-1
When /BYTE=VIH, /CE=/OE=VIL , D15/A-1 is output status. At this time, input signal must not be applied.
9
May 1997 , Rev.6.1

9 Page





Information Total 14 Pages
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