M5K4164ANL-15 Datasheet PDF - Mitsubishi
| Part Number | M5K4164ANL-15 | |
| Description | 64K-Bit DRAM | |
| Manufacturers | Mitsubishi | |
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MITSUBISHI-LSls
MsK4164ANL-12, -15
65 536-BIT (65 536-WORD BY I-BIT) DYNAMIC RAM
DESCRIPTION
This is a family of 65536-word by 1-bit dynamic RAMs,
fabricated with the high performance N-channel silicongate
MOS process, and is ideal for large-capacity memory
systems where high speed, low power dissipation, and low
costs are essential_ The use of double-layer polysilicon
process technology and a single-transistor dynamic storage
cell privide high circuit density at reduced costs, and the
use of dynamic circuitry including sense amplifiers assures
low power dissipation_ Multiplexed address inputs permit
both a reduction in pins to the 16-pin zigzag inline package
configuration and an increase in system densities_ The
M5K4164AN L operates on a 5V power supply using
the on-chip substrate bias generator_
PIN CONFIGURATION (TOP VIEW)
I1ADDRESS INPUT A6 -+
!COL~~R~:~~~~i CAS -+ 1]
INO CONNECTIONI NC
§J ~ [._!
DATA OUTPUT
Vss (OV)
WRITE CONTROL
INPUT
W -+
Ao -+
L-,
"91
;...;.
~
L~
,..-
L~
+- D
+- RAS
DATA INPUT
~~~O:~~~~~~
ADDRESS {
INPUTS
-, r :;-0 +-- A2 ADDRESS INPUT
A1 -+ flJ ~ ~:2
A7 --+ 131 ..!. L_
Vee (SV)
-~ UI :-=t-4 +- A }
A4 -+ 151 "-
s ADDRESS
-" D} +- AJ INPUTS
FEATURES
• High speed
Type name
M5K4164ANL-12
M5K4164ANL-15
Access time
lmaxl
Insl
120
150
Cycle time
(min)
Insl
220
260
Power dissipation
Itypl
ImWI
175
150
• 16 pin zigzag inline package
• Single 5V±10% supply
• Low standby power dissipation: 22mW (max)
• Low operating power dissipation:
M5K4164ANL-12 275mW (max)
M5K4164ANL-15 250mW (max)
• Unlatched output enables two-dimensional chip selec-
tion and extended page boundary
• Early-write operation gives common I/O capability
• Read-modify-write, RAS-only refresh, and page-mode
capabil ities
Outline 16P5A
• All input terminals have low input capaciatance and are
directly TTL-compatible
• Output is three-state and directly TTL-compatible
• 128 refresh cycles every 2ms
(16K dynamic RAMs M5K4116P, S compatible)
• CAS controlled output allows hidden refresh
• Output data can be held infinitely by CAS
APPLICATION
• Main memory unit for computers
• Refresh memory for CRT
BLOCK DIAGRAM
DATA INPUT
D
WRITE CONTROL INPUT Vi
COL~rRNo~f9~~3~ CAS
~.g~Mf9~~3f RAS
Vee ISV)
Vss 10V)
ADDRESS INPUTS
Ao
Al
A2
A3
A.
As
A7
MEMORY CELL
164 ROWS X 256 COLUMNSI
SENSE REFRESH AMPLIFIER
MEMORY CELL
164 ROWS X 256 COLUMNSI
COLUMN DECODER
MEMORY CELL
194 ROWS x 256 COLUMNSI
SENSE REFRESH AMPLIFIER
MEMORY CELL
164 ROWS X 256 COLUMNSI
COLUMN DECODER
l-
Sua:
U
..J
0a:
Iz-
u0
g
2 Q DATA PUTPUT
• MITSUBISHI
. . . . ELECTRIC
2-45
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MITSUBISHI LSls
MSK4164ANL-12, -15
65 536-BIT (65 536-WORD BY 1-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Page-Mode Cycle)
(Ta =0 - 70·C, Vcc=5V ± 10%. Vss=OV, unlessotherwisenoted,Seenotcs5,6i:1lld7)
Symbol
Parameter
tCRF
I W(AASH)
IW(AASL)
I W(CASL)
t W(CASH)
I h IAAS-CAS)
I h (CAS- AAS)
Id (CAS-AAS)
IdIAAS-CASI
I SU(AA-AAS)
t SU(CA-CAS)
Ih(AAS-AA)
I h (CAS-CAl
I h IAAS-CA)
I THL
t TLH
Refresh cycle time
AAS high pulse width
RAS low pulse width
CAS low pulse width
CAS high pulse width
CAS hold time after RAS
RAS hold time after CAS
Delay time, CAS to RAS
Delay time. AAS to CAS
Row address setup time before RAS
Column address setup time before CAS
Row address hold time after RAS
Column address hold time after CAS
Column address hold time after RAS
Transition time
INote 81
INote 91
INote 101
Alternative
Symbol
I AEF
lAP
I AAS
ICAS
ICPN
ICSH
I RSH
I CAP
1 ACO
I ASA
I ASC
I AAH
I CAH
IAA
IT
M5K4164ANL-12
limits
M'n M{lx
2
90
120 10000
60 00
30
120
60
-20
25 60
0
0
15
20
90
3 35
M5K4164ANL-15
Limits
Mm Ma'
2
100
150 10000
75 00
35
150
75
-20
30 75
0
-0-
20
25
95
3 50
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 5
10:
An initial pause of 500,us is required after power-ulJ followed by any eight RAS or RAS/CAS cycles before proper device operation IS achiever!
= =The switching characteristics are defined as t THL t TLH 5ns.
Reference levels of input signals are VI H min. and VI L max. Reference levels for transition time are also between VI Hand V il .
Except for page-mode.
td(CA·S-RASI requirement is only applicable for RAS/CAS cycles preceeded by a CAS only cycle (i.e., For systems where CAS has not been decoded with RAS.)
Operation within the td eRAS-CAS) max limit insures that t a (RAS) max can be met. td (RAS-CAS)maX is specified reference pOint nnlY,ii
td (RAS-CAS) is greater than the specified td (RAS-CAS) max limit, then access time is controlled exclusively by ta (CAS)·
td (RAS-CAs)min = th (RAS-RA)min + 2t THL(t TLH) + t su (CA-CAS)m"ln_
SWITCHING CHARACTERISTICS (Ta~0-70·C. Vcc=5V±10%, VSs=OV, unlessotherwisenoted)
Read Cycle
Symbol
ICA
Isu (A-CAS)
Ih (CAS-A)
Ih I AAS-A)
Idls (CAS)
la (CAS)
la (AAS)
Parameter
Read cycle time
Read setup time before CAS
Read hold time after CAS
Read hold time after RAS
Output disable time
CAS access time
RAS access time
INote t 11
INote 111
INote 121
INote 131
INote 141
Alternative
Symbol
lAC
lACS
I ACH
IAAH
IOFF
I CAC
I AAC
M5K4164ANL-12
Limits
Min Ma'
220
0
0
10
0 35
60
<120
M5K4164ANL-15
Limits
Min M"
260
0
0
20
0 40
75
150
Unit
ns
ns
ns
ns
ns
ns
ns
Note 11
Note 12
Note 13·
Note 14
Either th (RAS-R) or th (CAS-R) must be satisfied for a read cycle.
tdls (CAS)max defines the time at which the output achieves the open circuit condition and is not reference to VOH or VOL
This is the value when td (RAS-CAS)~td (RAS-CAS) max. Test conditions; Load:::: 2T TL, CL :::: 100pF
This is the value when td lRAS.CAS)< td (RAS-CAS)max. When td (RAS·CAS)~td (RAS-CAS)max. ta (RAS) will increase by the amount that
td (RAS-CAS) exceeds the value shown. Test conditions, Load = 2T TL. CL = 100pF
Write Cycle
Symbol
Parameter
lew
Isu (W-CAS)
Ih (CAS-W)
Ih (AAS-W)
Ih (W-AAS)
Ih (W-CAS)
Iw(W)
Isu (o-CAsl
Ih (CAS-OI
Ih (AAS-O)
Write cycle time
Write setup time before CAS
Write hold time after CAS
Write hold time after RAS
RAS hold time after write
CAS hold time after write
Write pulse width
Data-in setup time before CAS
Data-in hold time after CAS
Data-in hold time after RAS
INote 171
Alternative
SymQol
lAC
I WCS
IWCH
I WCA
I AWL
ICWL
Iwp
lOS
IOH
IOHA
M5K4164ANL-12
Limits
Min Max
220
-5
40
90
40
40
40
0
40
90
M5K4164ANL-15
Limits
Min Ma'
260
-5
45
95
45
45
45
0
45
95
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
• MITSUBISHI
.... ELECTRIC
2-49
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Featured Datasheets
| Part Number | Description | MFRS |
| M5K4164ANL-12 | The function is 64K-Bit DRAM. Mitsubishi | |
| M5K4164ANL-15 | The function is 64K-Bit DRAM. Mitsubishi | |
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