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PDF DS83C530 Data sheet ( Hoja de datos )
| Número de pieza | DS83C530 | |
| Descripción | EPROM/ROM Microcontrollers | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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DS87C530/DS83C530
EPROM/ROM Microcontrollers with
Real-Time Clock
www.maxim-ic.com
FEATURES
80C52 Compatible
8051 Instruction-Set Compatible
Four 8-Bit I/O Ports
Three 16-Bit Timer/Counters
256 Bytes Scratchpad RAM
Large On-Chip Memory
16kB EPROM (OTP)
1kB Extra On-Chip SRAM for MOVX
ROMSIZE Features
Selects Effective On-Chip ROM Size from
0 to 16kB
Allows Access to Entire External Memory Map
Dynamically Adjustable by Software
Useful as Boot Block for External Flash
Nonvolatile Functions
On-Chip Real-Time Clock with Alarm Interrupt
Battery Backup Support of 1kB SRAM
High-Speed Architecture
4 Clocks/Machine Cycle (8051 = 12)
Runs DC to 33MHz Clock Rates
Single-Cycle Instruction in 121ns
Dual Data Pointer
Optional Variable Length MOVX to Access
Fast/Slow RAM /Peripherals
Power Management Mode
Programmable Clock Source Saves Power
Runs from (crystal/64) or (crystal/1024)
Provides Automatic Hardware and Software Exit
EMI Reduction Mode Disables ALE
Two Full-Duplex Hardware Serial Ports
High Integration Controller Includes:
Power-Fail Reset
Early-Warning Power-Fail Interrupt
Programmable Watchdog Timer
14 Total Interrupt Sources with Six External
PIN CONFIGURATIONS
TOP VIEW
7
1
8
47
46
DALLAS
DS87C530
DS83C530
20 34
21 33
PLCC, WINDOWED CLCC
39 27
40 26
DALLAS
DS87C530
DS83C530
52 14
1 13
TQFP
The High-Speed Microcontroller User’s Guide must
be used in conjunction with this data sheet. Download it
at: www.maxim-ic.com/microcontrollers.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 071107
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DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
PIN DESCRIPTION (continued)
PIN
PLCC TQFP
38 31
39 32
50 43
NAME
FUNCTION
PSEN
ALE
P0.0 (AD0)
Program Store-Enable Output. This active-low signal is a chip enable for optional
external ROM memory. PSEN provides an active-low pulse and is driven high when
external ROM is not being accessed.
Address Latch-Enable Output. This pin latches the external address LSB from the
multiplexed address/data bus on Port 0. This signal is commonly connected to the
latch enable of an external 373 family transparent latch. ALE has a pulse width of
1.5 XTAL1 cycles and a period of four XTAL1 cycles. ALE is forced high when the
device is in a Reset condition. ALE can be disabled and forced high by writing
ALEOFF = 1 (PMR.2). ALE operates independently of ALEOFF during external
memory accesses.
49 42 P0.1 (AD1) Port 0 (AD0–AD7), I/O. Port 0 is an open-drain, 8-bit, bidirectional I/O port. As an
48 41 P0.2 (AD2) alternate function Port 0 can function as the multiplexed address/data bus to access
off-chip memory. During the time when ALE is high, the LSB of a memory address
47 40 P0.3 (AD3) is presented. When ALE falls to a logic 0, the port transitions to a bidirectional data
46 39 P0.4 (AD4) bus. This bus is used to read external ROM and read/ write external RAM memory
or peripherals. When used as a memory bus, the port provides active high drivers.
45 38 P0.5 (AD5) The reset condition of Port 0 is tri-state. Pullup resistors are required when using
44 37 P0.6 (AD6) Port 0 as an I/O port.
43 36 P0.7 (AD7)
3 48 P1.0
Port 1, I/O. Port 1 functions as both an 8-bit, bidirectional I/O port and an alternate
functional interface for Timer 2 I/O, new External Interrupts, and new Serial Port 1.
4 49 P1.1 The reset condition of Port 1 is with all bits at a logic 1. In this state, a weak pullup
holds the port high. This condition also serves as an input mode, since any external
circuit that writes to the port will overcome the weak pullup. When software writes a
5 50 P1.2 0 to any port pin, the device will activate a strong pulldown that remains on until
either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 will
cause a strong transition driver to turn on, followed by a weaker sustaining pullup.
6 51 P1.3 Once the momentary strong driver turns off, the port again becomes the output high
(and input) state. The alternate modes of Port 1 are outlined as follows.
7 52 P1.4
Port Alternate
Function
P1.0 T2
External I/O for Timer/Counter 2
8 1 P1.5 P1.1 T2EX
Timer/Counter 2 Capture/Reload Trigger
P1.2 RXD1
Serial Port 1 Input
P1.3 TXD1
9 2 P1.6 P1.4 INT2
P1.5 INT3
Serial Port 1 Output
External Interrupt 2 (Positive Edge Detect)
External Interrupt 3 (Negative Edge Detect)
P1.6 INT4
10 3 P1.7 P1.7 INT5
External Interrupt 4 (Positive Edge Detect)
External Interrupt 5 (Negative Edge Detect)
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DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
automatically to occur once per second, once per minute, once per hour, or once per day. Enabling
interrupts with no match will generate an interrupt 256 times per second.
Software enables the timekeeper oscillator using the RTC enable bit in the RTC Control register (F9h).
This starts the clock. It can disable the oscillator to preserve the life of the backup energy-source if
unneeded. Values in the RTC Control register are maintained by the backup source through power failure.
Once enabled, the RTC maintains time for the life of the backup source even when VCC is removed.
The RTC will maintain an accuracy of 2 minutes per month at 25C. Under no circumstances are
negative voltages, of any amplitude, allowed on any pin while the device is in data retention mode
(VCC < VBAT). Negative voltages will shorten battery life, possibly corrupting the contents of internal
SRAM and the RTC.
Figure 2. Real-Time Clock
NONVOLATILE RAM
The 1k x 8 on-chip SRAM can be nonvolatile if an external backup energy source is used. This allows the
device to log data or to store configuration settings. Internal switching circuits will detect the loss of VCC
and switch SRAM power to the backup source on the VBAT pin. The 256 bytes of direct RAM are not
affected by this circuit and are volatile.
CRYSTAL AND BACKUP SOURCES
To use the unique functions of the DS87C530/DS83C530, a 32.768kHz timekeeping crystal and a backup
energy source are needed. The following describes guidelines for choosing these devices.
Timekeeping Crystal
The DS87C530/DS83C530 can use a standard 32.768kHz crystal as the RTC time base. There are two
versions of standard crystals available, with 6pF and 12.5pF load capacitance. The tradeoff is that the 6pF
uses less power, giving longer life while VCC is off, but is more sensitive to noise and board layout. The
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| PDF Descargar | [ Datasheet DS83C530.PDF ] | |
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