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PDF DS87C520 Data sheet ( Hoja de datos )
| Número de pieza | DS87C520 | |
| Descripción | EPROM/ROM High-Speed Microcontrollers | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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DS87C520/DS83C520
EPROM/ROM High-Speed Microcontrollers
www.maxim-ic.com
FEATURES
80C52 Compatible
8051 Pin- and Instruction-Set Compatible
Four 8-Bit I/O Ports
Three 16-Bit Timer/Counters
256 Bytes Scratchpad RAM
Large On-Chip Memory
16kB Program Memory
1kB Extra On-Chip SRAM for MOVX
ROMSIZE Feature
Selects Internal ROM Size from 0 to 16kB
Allows Access to Entire External Memory Map
Dynamically Adjustable by Software
Useful as Boot Block for External Flash
High-Speed Architecture
4 Clocks/Machine Cycle (8051 = 12)
Runs DC to 33MHz Clock Rates
Single-Cycle Instruction in 121ns
Dual Data Pointer
Optional Variable Length MOVX to Access
Fast/Slow RAM/Peripherals
Power Management Mode
Programmable Clock Source to Save Power
CPU Runs from (crystal/64) or (crystal/1024)
Provides Automatic Hardware and Software Exit
EMI Reduction Mode Disables ALE
Two Full-Duplex Hardware Serial Ports
High Integration Controller Includes:
Power-Fail Reset
Early-Warning Power-Fail Interrupt
Programmable Watchdog Timer
13 Interrupt Sources with Six External
Available in 40-pin PDIP, 44-Pin PLCC, 44-Pin
TQFP, and 40-Pin Windowed CERDIP
Factory Mask DS83C520 or EPROM (OTP)
DS87C520
The High-Speed Microcontroller User’s Guide must be used in
conjunction with this data sheet. Download it at:
www.maxim-ic.com/microcontrollers.
PIN CONFIGURATIONS
TOP VIEW
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 022207
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DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
PIN DESCRIPTION (continued)
PIN
DIP PLCC
TQFP
NAME
30 33 27 ALE
39 43
38 42
37 41
36 40
35 39
34 38
33 37
32 36
12
23
34
45
56
37 P0.0 (AD0)
36 P0.1 (AD1)
35 P0.2 (AD2)
34 P0.3 (AD3)
33 P0.4 (AD4)
32 P0.5 (AD5)
31 P0.6 (AD6)
30 P0.7 (AD7)
40 P1.0
41 P1.1
42 P1.2
43 P1.3
44 P1.4
FUNCTION
Address Latch Enable Output. The ALE functions as a clock to
latch the external address LSB from the multiplexed address/data bus
on Port 0. This signal is commonly connected to the latch enable of an
external 373 family transparent latch. ALE has a pulse width of 1.5
XTAL1 cycles and a period of four XTAL1 cycles. ALE is forced
high when the DS87C520/DS83C520 are in a reset condition. ALE
can also be disabled and forced high by writing ALEOFF = 1
(PMR.2). ALE operates independently of ALEOFF during external
memory accesses.
Port 0 (AD0–7), I/O. Port 0 is an open-drain, 8-bit, bidirectional I/O
port. As an alternate function Port 0 can function as the multiplexed
address/data bus to access off-chip memory. During the time when
ALE is high, the LSB of a memory address is presented. When ALE
falls to a logic 0, the port transitions to a bidirectional data bus. This
bus is used to read external ROM and read/write external RAM
memory or peripherals. When used as a memory bus, the port
provides active high drivers. The reset condition of Port 0 is tri-state.
Pullup resistors are required when using Port 0 as an I/O port.
Port 1, I/O. Port 1 functions as both an 8-bit, bidirectional I/O port
and an alternate functional interface for Timer 2 I/O, new External
Interrupts, and new Serial Port 1. The reset condition of Port 1 is with
all bits at a logic 1. In this state, a weak pullup holds the port high.
This condition also serves as an input state; a weak pullup holds the
port high. This condition also serves as an input mode, since any
external circuit that writes to the port will overcome the weak pullup.
When software writes a 0 to any port pin, the DS87C520/DS83C520
will activate a strong pulldown that remains on until either a 1 is
written or a reset occurs. Writing a 1 after the port has been at 0 will
cause a strong transition driver to turn on, followed by a weaker
sustaining pullup. Once the momentary strong driver turns off, the
port again becomes the output high (and input) state. The alternate
modes of Port 1 are out-lines as follows.
67
78
89
Port Alternate
Function
1
P1.5 P1.0 T2
External I/O for Timer/Counter 2
P1.1 T2EX
EX Timer/Counter 2 Capture/Reload Trigger
P1.2 RXD1
Serial Port 1 Input
2
P1.6 P1.3 TXD1
Serial Port 1 Output
P1.4 INT2
External Interrupt 2 (Positive Edge Detect)
P1.5 INT3
External Interrupt 3 (Negative Edge Detect)
3
P1.7 P1.6 INT4
External Interrupt 4 (Positive Edge Detect)
P1.7 INT5
External Interrupt 5 (Negative Edge Detect)
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5 Page 
DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
16kB internal program space. If software reconfigures the ROMSIZE register to 4kB (0000h–0FFFh) in
the current state, the device will immediately jump to external program execution because program code
from 4kB to 16kB (1000h–3FFFh) is no longer located on-chip. This could result in code misalignment
and execution of an invalid instruction. The recommended method is to modify the ROMSIZE register
from a location in memory that will be internal (or external) both before and after the operation. In the
above example, the instruction which modifies the ROMSIZE register should be located below the 4kB
(1000h) boundary, so that it will be unaffected by the memory modification. The same precaution should
be applied if the internal program memory size is modified while executing from external program
memory.
Off-chip memory is accessed using the multiplexed address/data bus on P0 and the MSB address on P2.
While serving as a memory bus, these pins are not I/O ports. This convention follows the standard 8051
method of expanding on-chip memory. Off-chip ROM access also occurs if the EA pin is a logic 0. EA
overrides all bit settings. The PSEN signal goes active (low) to serve as a chip enable or output enable
when Ports 0 and 2 fetch from external ROM.
Figure 2. ROM Memory Map
ROM SIZE ADJUSTABLE
DEFAULT = 16kB
ROM SIZE IGNORED
DATA MEMORY ACCESS
Unlike many 8051 derivatives, the DS87C520/DS83C520 contain on-chip data memory. They also
contain the standard 256 bytes of RAM accessed by direct instructions. These areas are separate. The
MOVX instruction accesses the on-chip data memory. Although physically on-chip, software treats this
area as though it was located off-chip. The 1kB of SRAM is between address 0000h and 03FFh.
Access to the on-chip data RAM is optional under software control. When enabled by software, the data
SRAM is between 0000h and 03FFh. Any MOVX instruction that uses this area will go to the on-chip
RAM while enabled. MOVX addresses greater than 03FFh automatically go to external memory through
Ports 0 and 2.
11 of 43
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS87C520.PDF ] | |
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