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PDF MKL25Z64VFT4 Data sheet ( Hoja de datos )
| Número de pieza | MKL25Z64VFT4 | |
| Descripción | Microcontroller | |
| Fabricantes | Freescale Semiconductor | |
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KL25 Sub-Family Reference Manual
Supports: MKL25Z32VFM4, MKL25Z64VFM4, MKL25Z128VFM4,
MKL25Z32VFT4, MKL25Z64VFT4, MKL25Z128VFT4,
MKL25Z32VLH4, MKL25Z64VLH4, MKL25Z128VLH4,
MKL25Z32VLK4, MKL25Z64VLK4, and MKL25Z128VLK4
Document Number: KL25P80M48SF0RM
Rev. 3, September 2012
1 page  
Section number
Title
Page
3.6.3 SRAM Configuration...................................................................................................................................75
3.7 Analog...........................................................................................................................................................................77
3.7.1 16-bit SAR ADC Configuration..................................................................................................................77
3.7.2 CMP Configuration......................................................................................................................................81
3.7.3 12-bit DAC Configuration...........................................................................................................................83
3.8 Timers...........................................................................................................................................................................84
3.8.1 Timer/PWM Module Configuration............................................................................................................84
3.8.2 PIT Configuration........................................................................................................................................87
3.8.3 Low-power timer configuration...................................................................................................................88
3.8.4 RTC configuration.......................................................................................................................................90
3.9 Communication interfaces............................................................................................................................................91
3.9.1 Universal Serial Bus (USB) FS Subsystem.................................................................................................91
3.9.2 SPI configuration.........................................................................................................................................96
3.9.3 I2C Configuration........................................................................................................................................97
3.9.4 UART Configuration...................................................................................................................................98
3.10 Human-machine interfaces (HMI)................................................................................................................................99
3.10.1 GPIO Configuration.....................................................................................................................................99
3.10.2 TSI Configuration........................................................................................................................................101
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................105
4.2 System memory map.....................................................................................................................................................105
4.3 Flash Memory Map.......................................................................................................................................................106
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................106
4.4 SRAM memory map.....................................................................................................................................................107
4.5 Bit Manipulation Engine...............................................................................................................................................107
4.6 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................108
4.6.1 Read-after-write sequence and required serialization of memory operations..............................................108
4.6.2 Peripheral Bridge (AIPS-Lite) Memory Map..............................................................................................109
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc.
5
5 Page 
Section number
Title
Page
14.3 Low-voltage detect (LVD) system................................................................................................................................237
14.3.1 LVD reset operation.....................................................................................................................................238
14.3.2 LVD interrupt operation...............................................................................................................................238
14.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................238
14.4 I/O retention..................................................................................................................................................................239
14.5 Memory map and register descriptions.........................................................................................................................239
14.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................240
14.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................241
14.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................242
Chapter 15
Low-Leakage Wakeup Unit (LLWU)
15.1 Introduction...................................................................................................................................................................245
15.1.1 Features........................................................................................................................................................245
15.1.2 Modes of operation......................................................................................................................................246
15.1.3 Block diagram..............................................................................................................................................247
15.2 LLWU signal descriptions............................................................................................................................................248
15.3 Memory map/register definition...................................................................................................................................248
15.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................249
15.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................250
15.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................251
15.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................252
15.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................253
15.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................255
15.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................257
15.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................258
15.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................260
15.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................261
15.4 Functional description...................................................................................................................................................262
15.4.1 LLS mode.....................................................................................................................................................263
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc.
11
11 Page | ||
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| PDF Descargar | [ Datasheet MKL25Z64VFT4.PDF ] | |
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