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PDF ATtiny11 Data sheet ( Hoja de datos )
| Número de pieza | ATtiny11 | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Utilizes the AVR® RISC Architecture
• High-performance and Low-power 8-bit RISC Architecture
– 90 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 8 MIPS Throughput at 8 MHz
• Nonvolatile Program and Data Memory
– 1K Byte of Flash Program Memory
In-System Programmable (ATtiny12)
Endurance: 1,000 Write/Erase Cycles (ATtiny11/12)
– 64 Bytes of In-System Programmable EEPROM Data Memory for ATtiny12
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
• Peripheral Features
– Interrupt and Wake-up on Pin Change
– One 8-bit Timer/Counter with Separate Prescaler
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
• Special Microcontroller Features
– Low-power Idle and Power-down Modes
– External and Internal Interrupt Sources
– In-System Programmable via SPI Port (ATtiny12)
– Enhanced Power-on Reset Circuit (ATtiny12)
– Internal Calibrated RC Oscillator (ATtiny12)
• Specification
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
• Power Consumption at 4 MHz, 3V, 25°C
– Active: 2.2 mA
– Idle Mode: 0.5 mA
– Power-down Mode: <1 µA
• Packages
– 8-pin PDIP and SOIC
• Operating Voltages
– 1.8 - 5.5V for ATtiny12V-1
– 2.7 - 5.5V for ATtiny11L-2 and ATtiny12L-4
– 4.0 - 5.5V for ATtiny11-6 and ATtiny12-8
• Speed Grades
– 0 - 1.2 MHz (ATtiny12V-1)
– 0 - 2 MHz (ATtiny11L-2)
– 0 - 4 MHz (ATtiny12L-4)
– 0 - 6 MHz (ATtiny11-6)
– 0 - 8 MHz (ATtiny12-8)
Pin Configuration
ATtiny11
PDIP/SOIC
(RESET) PB5
(XTAL1) PB3
(XTAL2) PB4
GND
1
2
3
4
8 VCC
7 PB2 (T0)
6 PB1 (INT0/AIN1)
5 PB0 (AIN0)
ATtiny12
PDIP/SOIC
(RESET) PB5
(XTAL1) PB3
(XTAL2) PB4
GND
1
2
3
4
8 VCC
7 PB2 (SCK/T0)
6 PB1 (MISO/INT0/AIN1)
5 PB0 (MOSI/AIN0)
8-bit
Microcontroller
with 1K Byte
Flash
ATtiny11
ATtiny12
Rev. 1006D–AVR–07/03
1
1 page  
Pin Descriptions
VCC
GND
Port B (PB5..PB0)
XTAL1
XTAL2
RESET
Clock Options
1006D–AVR–07/03
ATtiny11/12
The ATtiny12 AVR is supported with a full suite of program and system development
tools including: macro assemblers, program debugger/simulators, in-circuit emulators,
and evaluation kits.
Supply voltage pin.
Ground pin.
Port B is a 6-bit I/O port. PB4..0 are I/O pins that can provide internal pull-ups (selected
for each bit). On ATtiny11, PB5 is input only. On ATtiny12, PB5 is input or open-drain
output. The port pins are tri-stated when a reset condition becomes active, even if the
clock is not running. The use of pins PB5..3 as input or I/O pins is limited, depending on
reset and clock settings, as shown below.
Table 2. PB5..PB3 Functionality vs. Device Clocking Options
Device Clocking Option
External Reset Enabled
External Reset Disabled
PB5
Used(1)
Input(3)/I/O(4)
PB4
-(2)
-
PB3
-
-
External Crystal
-
Used
Used
External Low-frequency Crystal
-
Used
Used
External Ceramic Resonator
External RC Oscillator
-
Used
Used
-
I/O(5)
Used
External Clock
- I/O Used
Internal RC Oscillator
- I/O I/O
Notes:
1. “Used” means the pin is used for reset or clock purposes.
2. “-” means the pin function is unaffected by the option.
3. Input means the pin is a port input pin.
4. On ATtiny11, PB5 is input only. On ATtiny12, PB5 is input or open-drain output.
5. I/O means the pin is a port input/output pin.
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
Output from the inverting oscillator amplifier.
Reset input. An external reset is generated by a low level on the RESET pin. Reset
pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter
pulses are not guaranteed to generate a reset.
The device has the following clock source options, selectable by Flash fuse bits as
shown:
Table 3. Device Clocking Options Select
Device Clocking Option
ATtiny11 CKSEL2..0
External Crystal/Ceramic Resonator
111
External Low-frequency Crystal
110
External RC Oscillator
101
ATtiny12 CKSEL3..0
1111 - 1010
1001 - 1000
0111 - 0101
5
5 Page 
Register Indirect
Figure 9. Indirect Register Addressing
REGISTER FILE
0
ATtiny11/12
Z-register
30
31
The register accessed is the one pointed to by the Z-register (R31, R30).
Register Direct, Two Registers Figure 10. Direct Register Addressing, Two Registers
Rd and Rr
I/O Direct
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d
(Rd).
Figure 11. I/O Direct Addressing
1006D–AVR–07/03
Operand address is contained in 6 bits of the instruction word. n is the destination or
source register address.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ATtiny11.PDF ] | |
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