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PDF PIC12HV752 Data sheet ( Hoja de datos )
| Número de pieza | PIC12HV752 | |
| Descripción | Flash-Based 8-Bit CMOS Microcontrollers | |
| Fabricantes | Microchip | |
| Logotipo |  |
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PIC12F752/HV752
Data Sheet
8-Pin, Flash-Based 8-Bit
CMOS Microcontrollers
*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450.
Additional U.S. and foreign patents and applications may be issued or pending.
2011 Microchip Technology Inc.
Preliminary
DS41576B
1 page  
PIC12F752/HV752
TABLE 2:
PIC12F752/HV752 PIN SUMMARY (PDIP, SOIC, DFN)
RA0(5) 7
AN0
C1IN0+
C2IN0+
—
— IOC
Y COG1OUT1(2) DACOUT
REFOUT
RA1 6
RA2(5) 5
RA3(1) 4
RA4 3
AN1
AN2
—
AN3
C1IN0-
C2IN0-
C1OUT
C2OUT
—
C1IN1-
——
T0CKI CCP1
T1G(3)
T1G(2)
—
—
IOC
IOC
INT
IOC
IOC
RA5 2 — C2IN1- T1CKI — IOC
Y—
Y COG1OUT0(2)
Y(4) COG1FLT(3)
Y COG1FLT(2)
COG1OUT1(3)
Y COG1OUT0(3)
VREF+
—
—
—
—
—1—
—
——— —
—
—
—8—
—
——— —
—
—
* Alternate pin function.
Note 1: Input only.
2: Default pin function via the APFCON register.
3: Alternate pin function via the APFCON register.
4: RA3 pull-up is enabled when pin is configured as MCLR in Configuration Word.
5: The port pins for the primary COG1OUTx pins have High Power (HP) output drivers.
ICSPDAT
ICSPCLK
—
MCLR/VPP
CLKOUT
CLKIN
VDD
VSS
2011 Microchip Technology Inc.
Preliminary
DS41576B-page 5
5 Page 
2.0 MEMORY ORGANIZATION
2.1 Program Memory Organization
The PIC12F752/HV752 has a 13-bit program counter
capable of addressing an 8K x 14 program memory
space. Only the first 1K x 14 (0000h-03FFh) is
physically implemented. Accessing a location above
these boundaries will cause a wrap-around within the
first 1K x 14 space for PIC12F752/HV752. The Reset
vector is at 0000h and the interrupt vector is at 0004h
(see Figure 2-1).
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F752/HV752
CALL, RETURN
RETFIE, RETLW
PC<12:0>
13
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
0000h
PIC12F752/HV752
2.2 Data Memory Organization
The data memory (see Figure 2-2) is partitioned into four
banks, which contain the General Purpose Registers
(GPR) and the Special Function Registers (SFR). The
Special Function Registers are located in the first 32
locations of each bank. Register locations 40h-6Fh in
Bank 0 are General Purpose Registers, implemented as
static RAM. Register locations 70h-7Fh in Bank 0 are
Common RAM and shared as the last 16 addresses in
all Banks. All other RAM is unimplemented and returns
‘0’ when read. The RP<1:0> bits of the STATUS register
are the bank select bits.
RP1 RP0
00
Bank 0 is selected
01
Bank 1 is selected
10
Bank 2 is selected
11
Bank 3 is selected
Interrupt Vector
On-chip Program
Memory
Wraps to 0000h-03FFh
0004h
0005h
03FFh
0400h
1FFFh
2011 Microchip Technology Inc.
Preliminary
DS41576B-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PIC12HV752.PDF ] | |
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