MPC8306S Datasheet PDF - NXP Semiconductors
Part Number | MPC8306S | |
Description | PowerQUICC II Pro Integrated Communications Processor | |
Manufacturers | NXP Semiconductors | |
Logo | ||
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Technical Data
Document Number: MPC8306SEC
Rev. 1, 09/2011
MPC8306S
PowerQUICC II Pro Integrated
Communications Processor
Family Hardware Specifications
This document provides an overview of the MPC8306S
PowerQUICC II Pro processor features. The MPC8306S is
a cost-effective, highly integrated communications
processor that addresses the requirements of several
networking applications, including residential gateways,
modem/routers, industrial control, and test and measurement
applications. The MPC8306S extends current PowerQUICC
offerings, adding higher CPU performance, additional
functionality, and faster interfaces, while addressing the
requirements related to time-to-market, price, power
consumption, and board real estate. This document describes
the electrical characteristics of MPC8306S.
To locate published errata or updates for this document, refer
to the MPC8306S product summary page on our website
listed on the back cover of this document or contact your
local Freescale sales office.
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10
4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 12
6. DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8. Ethernet and MII Management . . . . . . . . . . . . . . . . . 21
9. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10. HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
11. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
12. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
13. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
14. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
15. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
16. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
17. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
18. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
19. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 44
20. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
21. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
22. System Design Information . . . . . . . . . . . . . . . . . . . 64
23. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 67
24. Document Revision History . . . . . . . . . . . . . . . . . . . 69
© 2011 Freescale Semiconductor, Inc. All rights reserved.
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Overview
— Six groups of interrupts with programmable priority
— External and internal interrupts directed to host processor
— Unique vector number for each interrupt source
• Universal serial bus (USB) dual-role controller
— Designed to comply with Universal Serial Bus Revision 2.0 Specification
— Supports operation as a stand-alone USB host controller
— Supports operation as a stand-alone USB device
— Supports high-speed (480-Mbps), full-speed (12-Mbps), and low-speed (1.5-Mbps) operations.
Low speed is only supported in host mode.
• Dual I2C interfaces
— Two-wire interface
— Multiple-master support
— Master or slave I2C mode support
— On-chip digital filtering rejects spikes on the bus
— I2C1 can be used as the boot sequencer
• DMA Engine
— Support for the DMA engine with the following features:
– Sixteen DMA channels
– All data movement via dual-address transfers: read from source, write to destination
– Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations
– Channel activation via one of two methods (for both the methods, one activation per
execution of the minor loop is required):
– Explicit software initiation
– Initiation via a channel-to-channel linking mechanism for continuous transfers
(independent channel linking at end of minor loop and/or major loop)
– Support for fixed-priority and round-robin channel arbitration
– Channel completion reported via optional interrupt requests
— Support for scatter/gather DMA processing
• DUART
— Two 2-wire interfaces (RxD, TxD)
– The same can be configured as one 4-wire interface (RxD, TxD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
• Serial peripheral interface (SPI)
— Master or slave support
• Power managemnt controller (PMC)
— Supports core doze/nap/sleep/ power management
— Exits low power state and returns to full-on mode when
– The core internal time base unit invokes a request to exit low power state
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
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