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PDF SSM9922EO Data sheet ( Hoja de datos )
| Número de pieza | SSM9922EO | |
| Descripción | DUAL N-CHANNEL ENHANCEMENT-MODE POWER MOSFETS | |
| Fabricantes | Silicon Standard | |
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SSM9922(G)EO
DUAL N-CHANNEL ENHANCEMENT-MODE POWER MOSFETS
Low on-resistance
Capable of 2.5V gate drive
Ideal for DC/DC battery applications
Description
G2
S2
S2
D2
TSSOP-8
Power MOSFETs from Silicon Standard provide the
designer with the best combination of fast switching,
ruggedized device design, ultra low on-resistance and
cost-effectiveness.
G1
S1
S1
D1
BV DSS
RDS(ON)
ID
20V
15mΩ
6.8A
D1 D2
G1 G2
S1 S2
This device is available with Pb-free lead finish (second-level interconnect) as SSM9922GEO.
Absolute Maximum Ratings
Symbol
Parameter
Rating
Units
VDS
VGS
ID @ TA=25°C
ID @ TA=70°C
IDM
PD @ TA=25°C
Drain-Source Voltage
Gate-Source Voltage
Drain Current3, VG S @ 4.5V
Drain Current3, VGS @ 4.5V
Pulsed Drain Current1
Total Power Dissipation
Linear Derating Factor
20
±12
6.8
5.4
25
1
0.008
V
V
A
A
A
W
W/°C
TSTG
TJ
Storage Temperature Range
Operating Junction Temperature Range
-55 to 150
-55 to 150
°C
°C
Thermal Data
Symbol
Rthj-a
Parameter
Thermal Resistance Junction-ambient3
Max.
Value
125
Unit
°C/W
Rev.2.01 12/06/2004
www.SiliconStandard.com
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1 page  
SSM9922(G)EO
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
Rev.2.01 12/06/2004
www.SiliconStandard.com
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