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PDF SSM20G45EGH Data sheet ( Hoja de datos )

Número de pieza SSM20G45EGH
Descripción N-channel Insulated-Gate Bipolar Transistor
Fabricantes Silicon Standard 
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SSM20G45EGH/J
N-channel Insulated-Gate Bipolar Transistor
PRODUCT SUMMARY
V CES
V CE(sat)
I CP
450V
5V typ.
130A
Pb-free; RoHS-compliant TO-251 (IPAK)
and TO-252 (DPAK)
G
D
S
TO-251 (suffix J)
G DS
TO-252 (suffix H)
ABSOLUTE MAXIMUM RATINGS
DESCRIPTION
The SSM20G45E acheives fast switching performance
with low gate charge without a complex drive circuit. It is
suitable for use in short-duration, high-current strobe
applications, such as still-camera flash.
The SSM20G45EGH is in a TO-252 package, which is
widely used for commercial and industrial surface-mount
applications.
The through-hole version, the SSM20G45EGJ in TO-251,
is available for vertical mounting, where a small footprint
is required on the board, and/or an external heatsink is
to be attached.
These devices are manufactured with an advanced process,
providing improved on-resistance and switching performance.
The gate has internal ESD protection.
Symbol
VCES
VGE
V GE P
ICP
PD
Parameter
Collector-emitter voltage
Gate-emitter voltage
Pulsed gate-emitter voltage
Pulsed collector current1
Total power dissipation, TC = 25°C
Value
450
±6
±8
130
20
Units
V
V
V
A
W
TSTG
TJ
Storage temperature range
Operating junction temperature range
THERMAL CHARACTERISTICS
Symbol
RΘJC
Parameter
Maximum thermal resistance, junction-case
-55 to 150
-55 to 150
°C
°C
Value
6
Units
°C/W
Notes:
1.Pulse width must be limited to avoid exceeding the safe operating area.
2.Pulse width <300us, duty cycle <2%.
5/16/2006 Rev.3.01
www.SiliconStandard.com
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SSM20G45EGH pdf
SSM20G45EGH/J
RG
G
+
5V
-
R
C
CV
CE
E
V
GE
TO THE
OSCILLOSCOPE
VCC=200V
VCE
90%
10%
VGE
td(on) tr
td(off) tf
Fig 9. Switching Time Test Circuit
Fig 10. Switching Time Waveform
G
+
1~3 mA
-
IG
V CE
C
V
GE
E
IC
TO THE
OSCILLOSCOPE
300V
Flasher
RG
VG
VCM = 300V
CM = 160uF
Vtrig
CM
+
_ VCM
IGBT
ICP = 130A
VG = 5V
Fig 11. Gate Charge Test Circuit
Fig 12. Application Test Circuit
5/16/2006 Rev.3.01
www.SiliconStandard.com
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