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PDF STP3010 Data sheet ( Hoja de datos )
| Número de pieza | STP3010 | |
| Descripción | Graphics Accelerator | |
| Fabricantes | SUN MICROELECTRONICS | |
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DATA SHEET
STP3010
July 1997
TGX
TurboGX™ Graphics Accelerator
DESCRIPTION
The STP3010 employs over 128,000 gates and implements an extended superset of previous GX architectures.
This chip provides an integral SBus interface, VRAM (video random-access memory) controller, a high-per-
formance math engine, plus a high-performance rendering (or drawing) engine. A complete graphics
accelerator can be built utilizing this chip, a clock device, VRAM, and a RAMDAC.
The STP3010 delivers an unparalleled level of integration that has allowed for its inclusion on a single-wide
SBus card. These products also make multi-headed acceleration a cost-effective reality. In addition to the
STP3010’s enhanced functionality, it offers high-resolution, off-screen memory, and multi-buffering
capabilities.
The STP3010 comes in a 223-pin ceramic pin grid array (CPGA) package.
FEATURES
• 100 percent compatibility with previous GX implementations
• Complete graphics accelerator in a single chip—just add RAM, a RAMDAC, and a clock device
• Large-scale integration in 0.6-micron custom CMOS
• Over 128,000 gates (~500,000 transistors)
• Integral high-performance rendering engine (up to 1600 Mpixels/s)
• Integral high-performance math engine (up to 100 MFLOPS)
• Integral asynchronous SBus interface (rendering and math performance independent of SBus clock rate)
• 1-Mb, 2-Mb, and 4-Mb VRAM support
• Integral high-performance VRAM controller
• New block mode support for high-speed solid fill
• Multi-vector processing capability for 2 vectors per command
• 8x16 Font FIFO
• FIFO and destination caches
• Multi-mode, multi-buffering support assuring MIT X11 compliance
• High-speed block copy for raster copies between buffers (eliminates visual anomalies, or tearing during double
buffering)
• Off-screen rendering support (improves window system performance)
• Enhanced programmable timing logic with support for flicker-free 76 Hz vertical refresh rates and multi-resolution
support including 1024x768, 1152x900, 1280x1024, and 1600x1280.
• Software driver for the device is included in Solaris 1.X and 2.X
1
1 page  
TGX
TurboGX™ Graphics Accelerator
Preliminary
STP3010
SIGNAL DESCRIPTIONS
SBus Interface
Signal
SB_ACK[2:0]
SB_AS
SB_CLK
SB_DB[31:0]
SB_IRQ5
SB_AB[23:0]
SB_RD
SB_RESET
SB_SEL
SB_SIZ[2:0]
Type
Output
Input
Input
Bidir
Output
Input
Input
Input
Input
Input
Description
SBus Transfer Acknowledge. These outputs indicate the conclusion of a
STP3010 SBus transaction. These lines are normally tristate and get driven
actively for only the concluding two cycles of a STP3010 SBus access.
SB Address Strobe. This input indicates that the SBus address, data, and
control signals are valid on the SBus. This pin has an internal pullup.
SBus Clock. This pin provides the basic timing for the STP3010’s SBus interface
logic. It should run in the 16-25 MHz range and should be symmetrical. This pin
has Schmidt trigger TTL input and an internal pullup.
SBus Data Bus. These pins contain data being transferred between the
STP3010 and the SBus. These pins have internal pullups.
SBus Interrupt for VBLANK event. This open-drain output indicates that the
STP3010 is requesting an SBus interrupt to indicate that occurrence of a
vertical blanking event.
SBus Address Bus. These pins contain the address of where data is being
transferred between the STP3010 and the SBus. These pins have internal
pullups.
SBus Read. This input indicates whether a SBus access is a read (high) or write
(low). This pin has an internal pullup.
SBus Reset. In general, this input causes the STP3010 to reset to a known
state.This pin has a schmidt trigger TTL input and an internal pullup.
SBus Slave Select. This input indicates that the SBus is selecting the STP3010
for access. This pin has an internal pullup.
SBus Size. These inputs tell the STP3010 the size of the access being made by
the SBus. These lines are only used when SB_SEL and SB_AS are active. The
STP3010 will return an error if the SB_SIZ lines indicate that a BURST cycle
has been requested. These pins have internal pullups.
Video Connector Interface
Signal
CSYNC
ID[2:0]
Type
Output
Input
Description
Composite Sync. This output is the combined sync signal for use by the monitor.
This output is synchronous with the oscillator input (MAIN OSC or ALT_OSC)
selected for video timing generation.
Identification. These inputs contain the monitor sense code taken from the
13W3 connector. This code shows up in the STP3010’s CONFIG register within
the FBC/FHC address space. These pins have internal pullups.
Whenever TEST_MODE = 0, ID[0] is used as the (uncomplemented) serial scan
chain input. ID[1] is used as a high-true scan chain shift enable.
July 1997
5
5 Page 
TGX
TurboGX™ Graphics Accelerator
Preliminary
STP3010
DC Characteristics
Symbol
VOH
VOL
RI
CI
Parameter
LD, BLANK, CS_DAC, CS_ROM, CSYNC,
OLx[A:H]
PDB_xx[7:0], WE_DSFx, Bx_SOEy,
CS_ALT, SCKx, VSYNC_TXD
RASx, CASx, OEx, WR[7:0], VA[8:0],
DSF_VSYNC
SB_DB[31:0], DOT_CLK
SB_ACK[2:0]
LD, BLANK, CS_DAC, CS_ROM, CSYNC,
OLx[A:H]
PDB_xx[7:0], WE_DSFx, Bx_SOEy,
CS_ALT, SCKx, VSYNC_TXD,
SB_DB[31:0], DOT_CLK
RASx, CASx, OEx, WR[7:0], VA[8:0],
DSF_VSYNC
SB_ACK[2:0]
All inputs
All inputs
Conditions
IOH= –2 mA
IOH = –4 mA
IOH = –6 mA
IOH = –4 mA*
IOH = –8 mA*
IOL = 2 mA
IOL = 4 mA
IOL = 6 mA
IOL = 8 mA
Input pullup
Min Max Unit
3.0 – V
3.0 – V
3.0 – V
2.4 – V
2.4 – V
0.8 – V
0.8 – V
0.8 – V
0.0 V
50 100 KΩ
– 12 pF
* All output pins, except SB_DB, SB_ACK, and DOT_CLK are driven with an LV-TTL driver. The intent is to draw less power and still remain TTL
compatible.
July 1997
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet STP3010.PDF ] | |
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