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PDF HS-201HSEH Data sheet ( Hoja de datos )
| Número de pieza | HS-201HSEH | |
| Descripción | BiCMOS Analog Switch | |
| Fabricantes | Intersil | |
| Logotipo |  |
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DATASHEET
Radiation Hardened High Speed, Quad SPST,
BiCMOS Analog Switch
HS-201HSRH, HS-201HSEH
The HS-201HSRH and HS-201HSEH are monolithic BiCMOS
analog switches featuring power-off high input impedance,
very fast switching speeds and low ON-resistance. Fabrication
on our DI RSG process ensures SEL immunity and only very
slight low dose rate sensitivity (ELDRS). These Class V/Q
devices are tested and guaranteed for 300krad(Si) total dose
performance.
Power-off high input impedance enables the use of this device
in redundant circuits without causing data bus signal
degradation. ESD protection, overvoltage protection, fast
switching times, low ON-resistance, and guaranteed radiation
hardness make the HS-201HSRH ideal for any space
application that requires improved switching performance.
Related Literature
• For a full list of related documents, visit our website
- HS-201HSRH product page
- HS-201HSEH product page
Features
• Electrically screened to DLA SMD# 5962-99618
• QML qualified per MIL-PRF-38535
• Radiation performance
- High dose rate (50-300rad(Si)/s). . . . . . . . . . . 300krad(Si)
- Low dose rate (0.01rad(SI)/s) . . . . . . . . . . . . . . 50krad(Si)
- SEL immune . . . . . . . . . . . . . . . . . . . . . . . . . DI RSG process
• Overvoltage protection (power on, switch off) . . . . . . . . ±30V
• Power off high impedance . . . . . . . . . . . . . . . . . . . . . . . . ±17V
• Fast switching times
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110ns (max)
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80ns (max)
• Low “ON” resistance . . . . . . . . . . . . . . . . . . . . . . . . 50Ωmax
• Pin compatible with industry standard 201 types
• Operating supply range . . . . . . . . . . . . . . . . . . . . ±10V to ±15V
• Wide analog voltage range (±15V supplies) . . . . . . . . . ±15V
• TTL compatible
Applications
• High speed multiplexing
• Sample and hold circuits
• Digital filters
• Operational amplifier gain switching networks
• Integrator reset circuits
Pin Configuration
HS1-201HSRH, HS1-201HSEH SBDIP (CDIP2-T16)
HS9-201HSRH, HS9-201HSEH FLATPACK (CDFP4-F16)
TOP VIEW
IN1 1
D1 2
S1 3
V- 4
GND 5
S4 6
D4 7
IN4 8
16 IN2
15 D2
14 S2
13 V+
12 NC
11 S3
10 D3
9 IN3
February 21, 2017
FN4874.4
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2000, 2006, 2013, 2014, 2017. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
HS-201HSRH, HS-201HSEH
Package Outline Drawing
For the most recent package outline drawing, see K16.A.
K16.A
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
Rev 2, 1/10
0.015 (0.38) PIN NO. 1
0.008 (0.20) ID OPTIONAL
12
0.050 (1.27 BSC)
PIN NO. 1
ID AREA
0.440 (11.18)
MAX
0.005 (0.13)
MIN
4
0.022 (0.56)
0.015 (0.38)
TOP VIEW
0.115 (2.92)
0.045 (1.14)
0.045 (1.14)
0.026 (0.66) 6
-C-
SEATING AND
BASE PLANE
0.285 (7.24)
0.245 (6.22)
0.13 (3.30)
MIN
LEAD FINISH
SIDE VIEW
0.009 (0.23)
0.004 (0.10)
-D-
0.370 (9.40)
0.250 (6.35)
0.03 (0.76) MIN
-H-
0.006 (0.15)
0.004 (0.10)
LEAD FINISH
BASE
METAL
0.009 (0.23)
0.004 (0.10)
0.019 (0.48)
0.015 (0.38)
0.0015 (0.04)
MAX
0.022 (0.56)
0.015 (0.38)
SECTION A-A
3
NOTES:
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark. Alternately, a tab may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the limits
of the tab dimension do not apply.
3. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
4. Measure dimension at all four corners.
5. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
6. Dimension shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
7. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
8. Controlling dimension: INCH.
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5
FN4874.4
February 21, 2017
5 Page | ||
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