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PDF ISL70003SEH Data sheet ( Hoja de datos )
| Número de pieza | ISL70003SEH | |
| Descripción | 6A Buck Regulator | |
| Fabricantes | Intersil | |
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DATASHEET
Radiation Hardened and SEE Hardened 3V to 13.2V, 6A
Buck Regulator
ISL70003SEH
The ISL70003SEH is a radiation and SEE hardened
synchronous buck regulator capable of operating over an
input voltage range of 3.0V to 13.2V. With integrated
MOSFETs, this highly efficient single chip power solution
provides a tightly regulated output voltage that is externally
adjustable from 0.6V to ~90% of the input voltage.
Continuous output load current capability is 6A for
TJ ≤+125°C and 3A for TJ ≤ +150°C.
The ISL70003SEH uses voltage mode control architecture
with feed-forward and switches at a selectable frequency of
500kHz or 300kHz. Loop compensation is externally
adjustable to allow for an optimum balance between stability
and output dynamic performance. The internal synchronous
power switches are optimized for high efficiency and
excellent thermal performance.
The chip features two logic-level disable inputs that can be
used to inhibit pulses on the phase (LXx) pins in order to
maximize efficiency based on the load current. The
ISL70003SEH also supports DDR applications and contains a
buffer amplifier for generating the VREF voltage.
High integration, best in class radiation performance and a
feature filled design make the ISL70003SEH an ideal choice
to power many of todays small form factor applications.
Applications
• FPGA, CPLD, DSP, CPU core and I/O supply voltages
• DDR memory supply voltages
• Low-voltage, high-density distributed power systems
Related Literature
• AN1897, ISL70003SEHEV1Z Evaluation Board
• AN1915, ISL70003SEH iSim:PE Model
• AN1913, Single Event Effects Testing of the ISL70003SEH,
3V to 13.2V, 6A Synchronous Buck Regulator
• AN1924, Total Dose Testing of the ISL70003SEH Radiation
Hardened Point Of Load Regulator
Features
• Acceptance tested to 50krad(Si) (LDR) wafer-by-wafer
• ±1% reference voltage over line, temperature and radiation
• Integrated MOSFETs 31mΩPFET/21mΩ NFET
- 95% peak efficiency
• Externally adjustable loop compensation
• Supports DDR applications (VTT tracks VDDQ/2)
- Buffer amplifier for generating VREF voltage
- 3A current sinking capability
• Grounded lid eliminates charge build up
• IMON pin for output current monitoring
• Adjustable analog soft-start
• Diode emulation for increased efficiency at light loads
• 500kHz or 300kHz operating frequency synch wording
• Monotonic start-up into prebiased load
• Full military temperature range operation
- TA = -55°C to +125°C
- TJ = -55°C to +150°C
• Radiation tolerance
- High dose rate (50-300rad(Si)/s). . . . . . . . . . . 100krad(Si)
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . 100krad(Si)*
* Limit established by characterization.
• SEE hardness
- SEB and SEL LETTH . . . . . . . . . . . . . . . . 86.4MeV•cm2/mg
- SET at LET 86.4MeV•cm2/mg . . . . . . . . . . . < ±3% ΔVOUT
- SEFI LETTH . . . . . . . . . . . . . . . . . . . . . . . . . 60MeV•cm2/mg
• Electrically screened to DLA SMD 5962-14203
FIGURE 1. POWER DISTRIBUTION SOLUTION FOR RAD HARD LOW
POWER FPGA’s
100
95
90
85
80
75
70
2.5V
5V
9V
65
60
3.3V
55
50
0123456
LOAD CURRENT (A)
FIGURE 2. EFFICIENCY vs LOAD, VIN = 12V, fSW = 300kHz
ALL OUTPUTS ACTIVE
May 12, 2016
FN8604.5
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013-2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL70003SEH
Pin Descriptions
PIN NUMBER PIN NAME ESD CIRCUIT
DESCRIPTION
1 NI 1 This pin is the non-inverting input to the internal error amplifier. Connect this pin to the REF pin for
typical applications or the BUFOUT pin for DDR memory power applications.
2 FB 1 This pin is the inverting input to the internal error amplifier. An external type III compensation network
should be connected between this pin and the VERR pin. The connection between the FB resistor divider
and the output inductor should be a Kelvin connection to optimize performance.
3
VERR
1 This pin is the output of the internal error amplifier. An external compensation network should be
connected between this pin and the FB pin.
4
POR_VIN
1 This pin is the power-on reset input to the IC. This is a comparator-type input with a rising threshold of
0.6V and programmable hysteresis. Driving this pin above 0.6V enables the IC. Bypass this pin to AGND
with a 10nF ceramic capacitor to mitigate SEE.
5
VREFA
3 This pin is the output of the internal linear regulator and the bias supply input to the internal analog
control circuitry. Locally filter this pin to AGND using a 0.47µF ceramic capacitor as close as possible to
the IC.
6
AVDD
5 This pin provides the supply for internal linear regulator of the ISL70003SEH. The supply to AVDD
should be locally bypassed using a ceramic capacitor. Tie AVDD to the PVINx pins.
7
AGND
1, 3 This pin is the analog ground associated with the internal analog control circuitry. Connect this pin
directly to the PCB ground plane.
8
DGND
2, 4 This pin is the ground associated with the internal digital control circuitry. Connect this pin directly to
the PCB ground plane.
9
VREF_OUTS
4 This pin is the output of the internal linear regulator and the supply input to the internal reference
circuit. Locally filter this pin to AGND using a 0.47µF ceramic capacitor as close as possible to the IC.
10
DVDD
6 This pin provides the supply for the internal linear regulator of the ISL70003SEH. The supply to DVDD
should be locally bypassed using a ceramic capacitor. Tie DVDD to the PVINx pin.
11
VREFD
4 This pin is the output of the internal linear regulator and the bias supply input to the internal digital
control circuitry. Locally filter this pin to DGND using a 0.47µF ceramic capacitor as close as possible
to the IC.
12
ENABLE
6 This pin is a logic-level enable input. Pulling this pin low powers down the chip by placing it into a very
low power sleep mode.
13
RT/CT
6 A resistor to VIN and a capacitor to GND provide feed-forward to keep a constant modulator gain of 4.8
as VIN varies.
14
FSEL
2 This pin is the oscillator frequency select input. Tie this pin to 5V to select a 300kHz nominal oscillator
frequency. Tie this pin to the PCB ground plane to select a 500kHz nominal oscillator frequency.
15
SYNC
2 This pin is the frequency synchronization input to the IC. This pin should be tied to GND to free-run from
the internal oscillator or connected to an external clock for external frequency synchronization.
16
SS_CAP
2 This pin is the soft-start input. Connect a ceramic capacitor from this pin to the PCB ground plane to set
the soft-start output ramp time in accordance with Equation 1:
tSS = CSS VREF ISS
(EQ. 1)
where:
tSS = soft-start output ramp time
CSS = soft-start capacitance
VREF = reference voltage (0.6V typical)
ISS = soft-start charging current (23µA typical)
Soft-start time is adjustable from approximately 2ms to 200ms. The range of the soft-start capacitor
should be 82nF to 8.2µF, inclusive.
17, 18, 19, 20, 21 GND
2 Connect this pin to the PCB ground plane.
22
PGOOD
6 This pin is the power-good output. This pin is an open-drain logic output that is pulled to DGND when
the output voltage is outside a ±11% typical regulation window. This pin can be pulled up to any voltage
from 0V to 13.2V, independent of the supply voltage. A nominal 1kΩ to 10kΩ pull-up resistor is
recommended. Bypass this pin to the PCB ground plane with a 10nF ceramic capacitor to mitigate SEE.
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5
FN8604.5
May 12, 2016
5 Page 
ISL70003SEH
Electrical Specifications Unless otherwise noted, VIN = AVDD = DVDD = PVINx = EN = 3V - 13.2V; GND = AGND = DGND = PGNDx =
GNDx = 0V; POR_VIN = FB = 0.65V; SYNC = LXx = Open Circuit; PGOOD is pulled up to VREFD with a 3k resistor; REF is bypassed to GND with a 220nF
capacitor; SS is bypassed to GND with a 100nF capacitor; IOUT = 0A; TA = TJ = +25°C. (Note 4). Boldface limits apply across the operating temperature
range, -55°C to +125°C; over a total ionizing dose of 100krad(Si) with exposure at a high dose rate of 50 - 300rad(Si)/s; or over a total ionizing dose of
50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 15)
TYP
MAX
(Note 15)
UNITS
POWER BLOCKS
Upper Device rDS(ON)
Lower Device rDS(ON)
LXx Output Leakage
PVINx = 3.0V
PVINx = 5.5V
PVINx = 3.0V
PVINx = 5.5V
EN = LXx = GND, Single LXx Output
170 420
120 310
90 240
60 210
1
700
600
455
425
3
mΩ
mΩ
mΩ
mΩ
µA
Dead Time
EN = GND, LXx = PVINx, Single LXx Output
1
Within a Single Power Block or between Power
Blocks (Note 14)
4
3
µA
ns
POWER-GOOD SIGNAL
Rising Threshold
Rising Hysteresis
Falling Threshold
Falling Hysteresis
Power-good Drive
Power-good Leakage
PROTECTION FEATURES
VFB as a % of VREF
VFB as a % of VREF
VFB as a % of VREF
VFB as a % of VREF
PVIN = 3V, PGOOD = 0.4V, EN = GND
PVIN = PGOOD = 13.2V
107 111
2 3.5
85 89
2 3.5
7.2
115
5
93
5
1
%
%
%
%
mA
µA
Undervoltage Protection
Undervoltage Trip Threshold
Undervoltage Recovery Threshold
Overcurrent Protection
VFB as a % of VREF, Test mode
VFB as a % of VREF, Test mode
71 75
86 90
79
94
%
%
Overcurrent Accuracy
BUFFER AMPLIFIER
ROCSETA, B = 6kΩ (IOC = 0.6A/LX) VIN = 12V
0.43
0.6
0.77
A/LX
Gain Bandwidth Product
CL = 1µF, ISOURCE = 1mA, AV = 1, VOUT = 1.25V
(Note 14)
200
kHz
Source Current Capability
20 mA
Sink Current Capability
250 400
µA
Offset Voltage
-4 0
4
mV
IMON CURRENT MONITOR
IMON Sense Time
145 215
300
ns
IMON Output Current Gain
ILOAD = 1A/Power Stage, LXx Off Time >300ns
100
IMON Gain Accuracy
ILOAD = 1A/Power Stage, LXx Off Time >300ns
-14
14
NOTES:
12. Typical values shown are not guaranteed.
13. The 0A to 6A output current range may be reduced by Minimum LXx On Time and Minimum LXx Off Time specifications.
14. Limits established by characterization or analysis and are not production tested.
15. Parameters with MIN and/or MAX limits are 100% tested at -55°C, +25°C and +125°C, unless otherwise specified.
µA/A
µA
Submit Document Feedback 11
FN8604.5
May 12, 2016
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