PDF XR17D152 Data sheet ( Hoja de datos )

Número de pieza	XR17D152
Descripción	UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
Fabricantes	Exar
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No Preview Available ! áç XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART JUNE 2004 GENERAL DESCRIPTION FEATURES REV. 1.2.0 The XR17D1521 (D152) is a monolithic dual PCI Bus Universal Asynchronous Receiver and Transmitter (UART) in Exar’s PCI Bus UART family. The device is designed to meet today’s 32-bit PCI Bus and high bandwidth requirement in communication systems. The global interrupt source register provides a complete interrupt status indication for both channels to speed up interrupt parsing. Each UART is independently controlled and has its own 16C550 compatible 5G (Fifth Generation) register set, transmit and receive FIFOs of 64 bytes, fully programmable transmit and receive FIFO trigger levels, transmit and receive FIFO level counters, automatic hardware flow control with programmable hysteresis, automatic software (Xon/Xoff) flow control, automatic half-duplex control output, wireless IrDA (Infrared Data Association) infrared encoder/ decoder, 8 multi-purpose inputs/outputs and a 16-bit general purpose timer/counter. NOTE: 1 Covered by U.S. Patents #5,649,122, #5,949,787 APPLICATIONS • Universal PCI Bus Add-in Card • Network Management • Factory Automation and Process Control • Ethernet Network to Serial Ports • Point-of-Sale Systems • Multi serial ports RS-232/RS-422/RS-485 Cards • High Performance Dual PCI UART • Universal PCI Bus Buffers - Auto-sense 3.3V and 5V Operation • 32-bit PCI Bus 2.3 Target Signalling Compliance • A Global Interrupt Source Register for both UARTs • Data Transfer in Byte, Word and Double-word • Data Read/Write Burst Operation • Each UART is independently controlled with: s 16C550 Compatible 5G Register Set s 64-byte Transmit and Receive FIFOs s Transmit and Receive FIFO Level Counters s Programmable TX and RX FIFO Trigger Level s Automatic RTS/CTS or DTR/DSR Flow Control s Automatic Xon/Xoff Software Flow Control s Automatic RS485 HDX Control Output with Selectable Turn-around Delay s Infrared (IrDA 1.0) Data Encoder/Decoder s Programmable Data Rate with Prescaler s Up to 6.25 Mbps Data Rate at 8X Sampling • Eight Multi-Purpose Inputs/outputs • A General Purpose 16-bit Timer/Counter • Sleep Mode with Automatic Wake-up • EEPROM Interface for PCI Configuration • Same package and pin-out as the XR17C152 (14x14x1.0 mm TQFP) FIGURE 1. BLOCK DIAGRAM 3.3V or 5V (PCI VI/O Power Supply) CLK (33 MHz) RST# AD[31:0] C/BE[3:0]# FRAME# IRDY# TRDY# DEVSEL# STOP# INTA# IDSEL PERR# SERR# PAR EECK EEDI EEDO EECS ENIR EN485# PCI Local Bus Interface Device Configuration Registers Configuration Space Registers EEPROM Interface 16-bit Timer/Counter UART Channel 0 UART Regs BRG 64 Byte TX FIFO TX & RX IR ENDEC 64 Byte RX FIFO UART Channel 1 UART Regs BRG 64 Byte TX FIFO TX & RX IR ENDEC 64 Byte RX FIFO VCC (Core Logic) GND TX0, RX0, DTR0#, DSR0#, RTS0#, CTS0#, CD0#, RI0# TX1, RX1, DTR1#, DSR1#, RTS1#, CTS1#, CD1#, RI1# Multi-pur.pose Inputs/Outputs Crystal Osc/Buffer MPIO0- MPIO7 XTAL1 XTAL2 TMRCK Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com 1 page áç REV. 1.2.0 XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART PIN DESCRIPTIONS NAME PIN # TYPE DESCRIPTION TMRCK ENIR EN485# TEST# 75 I 16-bit timer/counter external clock input. 74 I Global Infrared mode enable (active high). This pin is sampled during power up, following a hardware reset (RST#) or soft-reset (register RESET). It can be used to start up both UARTs in the infrared mode. The sampled logic state is transferred to MCR bit-6 in the UART. Software can override this pin there- after and enable or disable it. 65 I Global AutoRS485 half-duplex direction control enable (active low). During power up or reset, this pin is sampled and if it is a logic high, both UARTs are set for Auto RS485 Mode. Also, the Auto RS485 bit, FCTR[5], is set in both channels. Software can override this pin thereafter and enable or disable it. 79 I Factory Test. Connect to VCC for normal operation. VCC 54, 80 PWR 5V or 3.3V power supply for the core logic. This power supply determines the VOH level of the non-PCI bus interface outputs. Note that VCC ≥ VIO for normal device operation. See “Application Examples” on page 7. However, VCC must equal VIO if sleep mode is used. See Sleep Mode section on page 18. VIO 10, 22, 32, 43, PWR PCI bus I/O power supply - 3.3V or 5V, detected by the auto-sense circuitry of 89, 100 the XR17D152. This power supply determines the VOH level of the PCI bus interface outputs. (PCI 2.3 signalling compliant at both 3.3V and 5V operation, suitable for uni- versal form factor add-in card application.) GND 1, 11, 23, 33, PWR Power supply common, ground. 44, 53, 78, 88 NC 63, 64 No Connection. NOTE: Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain. 5 5 Page áç REV. 1.2.0 XR17D152 UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ADDRESS BITS TYPE DESCRIPTION RESET VALUE (HEX) 0x18h 31:0 RO Unimplemented Base Address Register (returns zeros) 0x00000000 0x1C 31:0 RO Unimplemented Base Address Register (returns zeros) 0x00000000 0x20 31:0 RO Unimplemented Base Address Register (returns zeros) 0x00000000 0x24 31:0 RO Unimplemented Base Address Register (returns zeros) 0x00000000 0x28 31:0 RO Reserved 0x00000000 0x2C 31:16 RWR1 Subsystem ID (write from external EEPROM by customer) 0x0000 15:0 RWR1 Subsystem Vendor ID (write from external EEPROM by cus- tomer) 0x0000 0x30 31:0 RO Expansion ROM Base Address (Unimplemented) 0x00000000 0x34 31:0 RO Reserved (returns zeros) 0x00000000 0x38 31:0 RO Reserved (returns zeros) 0x00000000 0x3C 31:24 RO Unimplemented MAXLAT 0x00 23:16 RO Unimplemented MINGNT 0x00 15:8 RO Interrupt Pin, use INTA#. 0x01 7:0 RWR Interrupt Line. 0xXX NOTE: RWR1=Read/Write from external EEPROM. RWR=Read/Write from AD[31:0]. RO= Read Only. WO=Write Only. 2.2 Device configuration Register Set The device configuration registers and a special way to access each of the UART’s transmit and receive data FIFOs are accessible directly from the PCI data bus. This provides easy programming of general operating parameters to the D152 UART and for monitoring the status of various functions. The registers occupy 1K of PCI bus memory address space. These addresses are offset onto the basic memory address, a value loaded into the Memory Base Address Register (BAR) in the PCI local bus configuration register set. These registers control or report on both channel UARTs functions that include interrupt control and status, 16-bit general purpose timer control and status, multipurpose inputs/outputs control and status, sleep mode control, soft- reset control, and device identification and revision, and others. The registers set is mapped into 2 address blocks where each UART channel occupies 512 bytes memory space for its own 16550 compatible configuration registers. The device configuration and control registers are embedded inside the UART channel zero’s address space between 0x0080 to 0x0093. All these registers can be accessed in 8, 16, 24 or 32 bit width depending on the starting address given by the host at beginning of the bus cycle. Transmit and receive data may be loaded or unloaded in 8, 16, 24 or 32 bit format to the register’s address. Every time a read or write operation is made to the transmit or receive register, its FIFO data pointer is automatically bumped to the next sequential data location either in byte, word or dword. One special case applies to the receive data unloading when reading the receive data together with its LSR register content. The host must read them in 16 or 32 bits format in order to maintain integrity of the data byte with its associated error tags. 11 11 Page

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