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What is CY14V256LA?

This electronic component, produced by the manufacturer "Cypress Semiconductor", performs the same function as "256-Kbit (32 K x 8) nvSRAM".


CY14V256LA Datasheet PDF - Cypress Semiconductor

Part Number CY14V256LA
Description 256-Kbit (32 K x 8) nvSRAM
Manufacturers Cypress Semiconductor 
Logo Cypress Semiconductor Logo 


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CY14V256LA
256-Kbit (32 K × 8) nvSRAM
256-Kbit (32 K × 8) nvSRAM
Features
35 ns access time
Internally organized as 32 K × 8
Hands off automatic STORE on power down with only a small
capacitor
STORE to QuantumTrap nonvolatile elements initiated by
software, device pin, or AutoStore on power down
RECALL to SRAM initiated by software or power up
Infinite read, write, and recall cycles
1 million STORE cycles to QuantumTrap
20 year data retention
Core VCC = 3.0 V to 3.6 V; I/O VCCQ = 1.65 V to 1.95 V
Industrial temperature
48-ball fine-pitch ball grid array (FBGA) package
Pb-free and restriction of hazardous substances (RoHS)
compliance
Functional Description
The Cypress CY14V256LA is a fast static RAM, with a
nonvolatile element in each memory cell. The memory is
organized as 32 K bytes of 8 bits each. The embedded
nonvolatile elements incorporate QuantumTrap technology,
producing the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while independent
nonvolatile data resides in the highly reliable QuantumTrap cell.
Data transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
For a complete list of related documentation, click here.
LogLiocgBicloBclkocDkiaDgiraagmram
A5
A6
A7
A8
A9
A 11
A 12
A 13
A 14
Quantum Trap
512 X 512
STORE
STATIC RAM
ARRAY
512 X 512
RECALL
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
VCC VCCQ VCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
HSB
SOFTWARE
DETECT
-A14 A2
OE
CE
WE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-76295 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 20, 2015

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CY14V256LA equivalent
CY14V256LA
are inhibited until HSB is returned HIGH by MPU or other
external source.
During any STORE operation, regardless of how it is initiated,
the CY14V256LA continues to drive the HSB pin LOW, releasing
it only when the STORE is complete. Upon completion of the
STORE operation, the nvSRAM memory access is inhibited for
tLZHSB time after HSB pin returns HIGH. Leave the HSB
unconnected if it is not used.
Hardware RECALL (Power-Up)
During power up or after any low-power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
During this time, HSB is driven LOW by the HSB driver.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14V256LA Software
STORE cycle is initiated by executing sequential CE or OE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the Software STORE cycle, the following read
sequence must be performed:
1. Read Address 0x0E38 Valid READ
2. Read Address 0x31C7 Valid READ
3. Read Address 0x03E0 Valid READ
4. Read Address 0x3C1F Valid READ
5. Read Address 0x303F Valid READ
6. Read Address 0x0FC0 Initiate STORE Cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE or OE controlled read operations
must be performed:
1. Read Address 0x0E38 Valid READ
2. Read Address 0x31C7 Valid READ
3. Read Address 0x03E0 Valid READ
4. Read Address 0x3C1F Valid READ
5. Read Address 0x303F Valid READ
6. Read Address 0x0C63 Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
Table 1. Mode Selection
CE WE
HX
LH
LL
LH
OE
A14–A0[1]
Mode
I/O
Power
X
X
Not selected Output High Z
Standby
L
X
Read SRAM
Output data
Active
X
X
Write SRAM
Input data
Active
L
0x0E38
Read SRAM
Output data
Active [2]
0x31C7
Read SRAM
Output data
0x03E0
Read SRAM
Output data
0x3C1F
Read SRAM
Output data
0x303F
Read SRAM
Output data
0x0B45
AutoStore
Output data
Disable
Notes
1. While there are 15 address lines on the CY14V256LA, only the 13 address lines (A14–A2) are used to control software modes. Rest of the address lines are don’t care.
2. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document Number: 001-76295 Rev. *D
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Featured Datasheets

Part NumberDescriptionMFRS
CY14V256LAThe function is 256-Kbit (32 K x 8) nvSRAM. Cypress SemiconductorCypress Semiconductor

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