|
|
PDF CY7C1329H Data sheet ( Hoja de datos )
| Número de pieza | CY7C1329H | |
| Descripción | 2-Mbit Pipelined Sync SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY7C1329H (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
CY7C1329H
2-Mbit (64 K × 32) Pipelined Sync SRAM
2-Mbit (64 K × 32) Pipelined Sync SRAM
Features
■ Registered inputs and outputs for pipelined operation
■ 64 K × 32 common I/O architecture
■ 3.3 V core power supply
■ 2.5 V/3.3 V I/O operation
■ Fast clock-to-output times
❐ 4.0 ns (for 133-MHz device)
■ Provide high-performance 3-1-1-1 access rate
■ User-selectable burst counter supporting Intel Pentium®
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed write
■ Asynchronous output enable
■ Offered in JEDEC-standard lead-free 100-pin TQFP package
■ “ZZ” Sleep Mode Option
Functional Description
The CY7C1329H SRAM integrates 64 K × 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE1), depth-expansion
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,
ADSP, and ADV), Write Enables (BW[A:D] and BWE), and Global
Write (GW). Asynchronous inputs include the Output Enable
(OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. This part supports Byte Write
operations (see Pin Definitions on page 4 and Truth Table on
page 7 for further details). Write cycles can be one to four bytes
wide as controlled by the Byte Write control inputs. GW when
active LOW causes all bytes to be written.
The CY7C1329H operates from a +3.3 V core power supply
while all outputs operate with either a +2.5 V or +3.3 V supply.
All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
For a complete list of related documentation, click here.
Logic Block Diagram
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BWD
BWC
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ADDRESS
REGISTER
2 A[1:0]
Q1
BURST
COUNTER
CLR AND Q0
LOGIC
DQD
BYTE
WRITE REGISTER
DQC
BYTE
WRITE REGISTER
DQB
BYTE
WRITE REGISTER
DQA
BYTE
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
DQD
BYTE
WRITE DRIVER
DQC
BYTE
WRITE DRIVER
DQB
BYTE
WRITE DRIVER
DQA
BYTE
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
INPUT
REGISTERS
ZZ SLEEP
CONTROL
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05673 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 20, 2014
1 page  
CY7C1329H
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock.
The CY7C1329H supports secondary cache in systems utilizing
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486 processors. The linear
burst sequence is suited for processors that utilize a linear burst
sequence. The burst order is user selectable, and is determined
by sampling the MODE input. Accesses can be initiated with
either the Processor Address Strobe (ADSP) or the Controller
Address Strobe (ADSC). Address advancement through the
burst sequence is controlled by the ADV input. A two-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All Writes are simplified with on-chip synchronous
self-timed Write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1 is
HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) CE1, CE2, CE3 are all asserted active, and (3) the Write
signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if
CE1 is HIGH. The address presented to the address inputs (A)
is stored into the address advancement logic and the address
register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
output registers. At the rising edge of the next clock the data is
allowed to propagate through the output register and onto the
data bus within tCO if OE is active LOW. The only exception
occurs when the SRAM is emerging from a deselected state to
a selected state, its outputs are always tri-stated during the first
cycle of the access. After the first cycle of the access, the outputs
are controlled by the OE signal. Consecutive single Read cycles
are supported. Once the SRAM is deselected at clock rise by the
chip select and either ADSP or ADSC signals, its output will
tri-state immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1,
CE2, CE3 are all asserted active. The address presented to A is
loaded into the address register and the address advancement
logic while being delivered to the RAM array. The Write signals
(GW, BWE, and BW[A:D]) and ADV inputs are ignored during this
first cycle.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ inputs is written into the corresponding
address location in the memory array. If GW is HIGH, then the
Write operation is controlled by BWE and BW[A:D] signals. The
CY7C1329H provides Byte Write capability that is described in
the Write Cycle Descriptions table. Asserting the Byte Write
Enable input (BWE) with the selected Byte Write (BW[A:D]) input,
will selectively write to only the desired bytes. Bytes not selected
during a Byte Write operation will remain unaltered. A
synchronous self-timed Write mechanism has been provided to
simplify the Write operations.
Because the CY7C1329H is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As a
safety precaution, DQs are automatically tri-stated whenever a
Write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted
HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the
appropriate combination of the Write inputs (GW, BWE, and
BW[A:D]) are asserted active to conduct a Write to the desired
byte(s). ADSC-triggered Write accesses require a single clock
cycle to complete. The address presented to A is loaded into the
address register and the address advancement logic while being
delivered to the memory array. The ADV input is ignored during
this cycle. If a global Write is conducted, the data presented to
DQ is written into the corresponding address location in the
memory core. If a Byte Write is conducted, only the selected
bytes are written. Bytes not selected during a Byte Write
operation will remain unaltered. A synchronous self-timed Write
mechanism has been provided to simplify the Write operations.
Because the CY7C1329H is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As a
safety precaution, DQs are automatically tri-stated whenever a
Write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1329H provides a two-bit wraparound counter, fed by
A1:A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed
specifically to support Intel Pentium applications. The linear
burst sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.Asserting ADV LOW at clock rise will
automatically increment the burst counter to the next address in
the burst sequence. Both Read and Write burst operations are
supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
CE3, ADSP, and ADSC must remain inactive for the duration of
tZZREC after the ZZ input returns LOW.
Document Number: 38-05673 Rev. *H
Page 5 of 20
5 Page 
Switching Characteristics
Over the Operating Range
Parameter [12, 13]
Description
tPOWER
Clock
tCYC
tCH
tCL
Output Times
tCO
tDOH
tCLZ
tCHZ
tOEV
tOELZ
tOEHZ
Set-up Times
tAS
tADS
tADVS
tWES
tDS
tCES
Hold Times
tAH
tADH
tADVH
tWEH
tDH
tCEH
VDD(typical) to the First Access [14]
Clock Cycle Time
Clock HIGH
Clock LOW
Data Output Valid after CLK Rise
Data Output Hold after CLK Rise
Clock to Low Z [15, 16, 17]
Clock to High Z [15, 16, 17]
OE LOW to Output Valid
OE LOW to Output Low Z [15, 16, 17]
OE HIGH to Output High Z [15, 16, 17]
Address Set-up before CLK Rise
ADSC, ADSP Set-up before CLK Rise
ADV Set-up before CLK Rise
GW, BWE, BW[A:D] Set-up before CLK Rise
Data Input Set-up before CLK Rise
Chip Enable Set-Up before CLK Rise
Address Hold after CLK Rise
ADSP, ADSC Hold after CLK Rise
ADV Hold after CLK Rise
GW, BWE, BW[A:D] Hold after CLK Rise
Data Input Hold after CLK Rise
Chip Enable Hold after CLK Rise
CY7C1329H
133 MHz
Min Max
1–
Unit
ms
7.5 – ns
3.0 – ns
3.0 – ns
– 4.0 ns
1.5 – ns
0 – ns
– 4.0 ns
– 4.5 ns
0 – ns
– 4.0 ns
1.5 – ns
1.5 – ns
1.5 – ns
1.5 – ns
1.5 – ns
1.5 – ns
0.5 – ns
0.5 – ns
0.5 – ns
0.5 – ns
0.5 – ns
0.5 – ns
Notes
12. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
13. Test conditions shown in (a) ofFigure 2 on page 10 unless otherwise noted.
14.
This part has
be initiated.
a
voltage
regulator
internally;
tPOWER
is
the
time
that
the
power
needs
to
be
supplied
above
VDD(minimum)
initially
before
a
Read
or
Write
operation
can
15. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 10. Transition is measured ± 200 mV from steady-state voltage.
16.
At any given voltage and temperature,
bus. These specifications do not imply
atObEuHsZciosnletesnstitohnancotOnEdLitZioann, dbutCt HreZfliescltepsasrtahmanetteCrLsZgtuoaeralimntieneadteobvuesr
contention
worst case
between SRAMs when
user conditions. Device
sharing the
is designed
same data
to achieve
High Z prior to Low Z under the same system conditions.
17. This parameter is sampled and not 100% tested.
Document Number: 38-05673 Rev. *H
Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet CY7C1329H.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY7C1329 | 64K x 32 Synchronous-Pipelined Cache RAM | Cypress Semiconductor |
| CY7C1329H | 2-Mbit Pipelined Sync SRAM | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |