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PDF CY7C1345G Data sheet ( Hoja de datos )
| Número de pieza | CY7C1345G | |
| Descripción | 4-Mbit Flow-Through Sync SRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1345G
4-Mbit (128K × 36) Flow-Through Sync SRAM
4-Mbit (128K × 36) Flow-Through Sync SRAM
Features
■ 128K × 36 common I/O
■ 3.3 V core power supply (VDD)
■ 2.5 V or 3.3 V I/O supply (VDDQ)
■ Fast clock-to-output times
❐ 8.0 ns (100 MHz version)
■ Provide high performance 2-1-1-1 access rate
■ User selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self timed write
■ Asynchronous output enable
■ Available in Pb-free 100-pin TQFP package
■ ZZ sleep mode option
Functional Description
The CY7C1345G is a 128K × 36 synchronous cache RAM
designed to interface with high speed microprocessors with
minimum glue logic. The maximum access delay from clock rise
is 8.0 ns (100 MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are gated
by registers controlled by a positive edge triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address pipelining chip enable (CE1), depth expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BWx, and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
The CY7C1345G enables either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses are initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) is active. Subsequent burst addresses
are internally generated as controlled by the Advance pin (ADV).
The CY7C1345G operates from a +3.3 V core power supply
while all outputs operate with either a +2.5 or +3.3 V supply. All
inputs and outputs are JEDEC standard JESD8-5 compatible.
For a complete list of related documentation, click here.
Selection Guide
Maximum access time
Maximum operating current
Maximum standby current
Description
100 MHz
8.0
205
40
Unit
ns
mA
mA
Errata: For information on silicon errata, see Errata on page 22. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05517 Rev. *P
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 7, 2016
1 page  
CY7C1345G
Pin Definitions
Name
I/O
Description
A0, A1, A
Input Address inputs used to select one of the 128 K address locations. Sampled at the rising edge of
synchronous the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the two
bit counter.
BWA, BWB,
BWC, BWD
GW
BWE
Input Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled
synchronous on the rising edge of CLK.
Input Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write
synchronous is conducted (all bytes are written, regardless of the values on BW[A:D] and BWE).
Input Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal is asserted LOW
synchronous to conduct a byte write.
CLK Input clock Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE1
Input
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
synchronous and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2
Input
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded.
CE3
Input
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.
OE Input Output enable, asynchronous input, active LOW. Controls the direction of the IO pins. When LOW,
asynchronous the IO pins act as outputs. When deasserted HIGH, IO pins are tristated and act as input data pins. OE
is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
Input Advance input signal, Sampled on the Rising Edge of CLK. When asserted, it automatically increments
synchronous the address in a burst cycle.
ADSP
ADSC
ZZ[2]
Input Address strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted
synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
Input Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted
synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
Input ZZ sleep input, active HIGH. When asserted HIGH places the device in a non-time critical sleep
asynchronous condition with data integrity preserved. During normal operation, this pin is low or left floating. ZZ pin has
an internal pull-down.
DQs,
DQPA,
DQPB,
DQPC,
DQPD
IO Bidirectional data IO lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins act as outputs. When HIGH, DQs and DQP[A:D]
are placed in a tristate condition.
Note
2. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see Errata on page 22.
Document Number: 38-05517 Rev. *P
Page 5 of 25
5 Page 
CY7C1345G
Maximum Ratings
Exceeding the maximum ratings may shorten the battery life of
the device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
DC voltage applied to outputs
in tristate ...........................................–0.5 V to VDDQ + 0.5 V
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(MIL-STD-883, method 3015) ................................. > 2001 V
Latch up current ..................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0 °C to +70 °C
–40 °C to +85 °C
VDD
VDDQ
3.3 V5% / 2.5 V – 5% to
+ 10%
VDD
Neutron Soft Error Immunity
Parameter
Description
Test
Conditions
Typ
Max*
Unit
LSBU
Logical single
bit upsets
25 °C
361 394 FIT/
Mb
LMBU
Logical multi
bit upsets
25 °C
0 0.01 FIT/
Mb
SEL
Single event
85 °C
0 0.1 FIT/
latch up
Dev
*staNtoistLicMalBU2,
or SEL events
95% confidence
occurred during
limit calculation.
testing; this column
For more details refer
represents a
to Application
Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial
Failure Rates”
Electrical Characteristics
Over the Operating Range
Parameter [10, 11]
Description
VDD
VDDQ
VOH
Power supply voltage
IO supply voltage
Output HIGH voltage
VOL Output LOW voltage
VIH Input HIGH voltage
VIL Input LOW voltage [10]
IX Input leakage current except ZZ
and MODE
Input current of MODE
Input current of ZZ
IOZ Output leakage current
IDD VDD operating supply current
Test Conditions
For 3.3 V IO, IOH = –4.0 mA
For 2.5 V IO, IOH = –1.0 mA
For 3.3 V, IO, IOL= 8.0 mA
For 2.5 V IO, IOL = 1.0 mA
For 3.3 V IO
For 2.5 V IO
For 3.3 V IO
For 2.5 V IO
GND VI VDDQ
Input = VSS
Input = VDD
Input = VSS
Input = VDD
GND VI VDDQ, output disabled
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
10 ns cycle,
100 MHz
Min
3.135
2.375
2.4
2.0
–
–
2.0
1.7
–0.3
–0.3
5
Max Unit
3.6 V
VDD
V
–V
–V
0.4 V
0.4 V
VDD + 0.3 V
VDD + 0.3 V
0.8
V
V
V
0.7 V
5 µA
–30 – µA
– 5 µA
–5 – µA
– 30 µA
–5 5 µA
– 205 mA
Notes
10. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
11. TPower up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 38-05517 Rev. *P
Page 11 of 25
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet CY7C1345G.PDF ] | |
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