PDF CY7C1362C Data sheet ( Hoja de datos )

Número de pieza	CY7C1362C
Descripción	9-Mbit Pipelined SRAM
Fabricantes	Cypress Semiconductor
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CY7C1360C CY7C1362C 9-Mbit (256K × 36/512K × 18) Pipelined SRAM 9-Mbit (256K × 36/512K × 18) Pipelined SRAM Features ■ Supports bus operation up to 200 MHz ■ Available speed grades: 200 MHz, and 166 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply (VDD) ■ 2.5 V/3.3 V I/O operation (VDDQ) ■ Fast clock-to-output times ❐ 3.0 ns (for 200 MHz device) ■ Provide high performance 3-1-1-1 access rate ■ User selectable burst counter supporting Intel Pentium® interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self-timed writes ■ Asynchronous output enable ■ Single cycle chip deselect ■ Available in Pb-free 100-pin TQFP package, non Pb-free 119-ball BGA package, and 165-ball FBGA package ■ TQFP available with 3-chip enable and 2-chip enable ■ IEEE 1149.1 JTAG-compatible boundary scan Functional Description The CY7C1360C/CY7C1362C SRAM integrates 256K × 36 and 512K × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining CchEip3[1e])n, abbulerst(CcEon1)t,rodl einppthu-tesxp(AanDsSioCn, chip enables (CE2 and ADSP, and ADV), write enables (BWX, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. Addresses and chip enables are registered at the rising edge of clock when either address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle.This part supports byte write operations (see Pin Definitions on page 8 and Truth Table on page 11 for further details). Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1360C/CY7C1362C operate from a +3.3 V core power supply while all outputs may operate with either a +2.5 or +3.3 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. For a complete list of related documentation, click here. Selection Guide Maximum access time Maximum operating current Maximum CMOS standby current Description 200 MHz 3.0 220 40 166 MHz 3.5 180 40 Unit ns mA mA Note 1. CE3 is for A version of TQFP (3 Chip Enable option) and 165-ball FBGA package only. 119-ball BGA is offered only in 2 Chip Enable. Cypress Semiconductor Corporation • 198 Champion Court Document Number: 38-05540 Rev. R • San Jose, CA 95134-1709 • 408-943-2600 Revised November 9, 2016 1 page CY7C1360C CY7C1362C Pin Configurations (continued) Figure 2. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (2 Chip Enables - AJ Version) DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1360C (256K × 36) 80 DQPB NC 79 DQB NC 78 DQB NC 77 76 75 VDDQ VSSQ DQB VDDQ VSSQ NC 74 DQB NC 73 DQB DQB 72 DQB DQB 71 70 69 VSSQ VDDQ DQB VSSQ VDDQ DQB 68 DQB DQB 67 VSS NC 66 NC 65 VDD VDD NC 64 ZZ 63 DQA VSS DQB 62 DQA DQB 61 60 59 VDDQ VSSQ DQA VDDQ VSSQ DQB 58 DQA DQB 57 DQA DQPB 56 DQA NC 55 54 53 VSSQ VDDQ DQA VSSQ VDDQ NC 52 DQA NC 51 DQPA NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1362C (512K × 18) 80 A 79 NC 78 NC 77 VDDQ 76 VSSQ 75 NC 74 DQPA 73 DQA 72 DQA 71 VSSQ 70 VDDQ 69 DQA 68 DQA 67 VSS 66 NC 65 VDD 64 ZZ 63 DQA 62 DQA 61 VDDQ 60 VSSQ 59 DQA 58 DQA 57 NC 56 NC 55 VSSQ 54 VDDQ 53 NC 52 NC 51 NC Document Number: 38-05540 Rev. R Page 5 of 38 5 Page CY7C1360C CY7C1362C Truth Table The Truth Table for CY7C1360C and CY7C1362C follows. [5, 6, 7, 8, 9, 10] Operation Deselect cycle, power-down Deselect cycle, power-down Deselect cycle, power-down Deselect cycle, power-down Deselect cycle, power-down Sleep mode, power-down READ cycle, begin burst READ cycle, begin burst WRITE cycle, begin burst READ cycle, begin burst READ cycle, begin burst READ cycle, continue burst READ cycle, continue burst READ cycle, continue burst READ cycle, continue burst WRITE cycle, continue burst WRITE cycle, continue burst READ cycle, suspend burst READ cycle, suspend burst READ cycle, suspend burst READ cycle, suspend burst WRITE cycle, suspend burst WRITE cycle, suspend burst Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK DQ None H X XL X LX X X L–H Tri-state None L L XL L XX X X L–H Tri-state None L X HL L XX X X L–H Tri-state None L L XL H LX X X L–H Tri-state None L X HL H LX X X L–H Tri-state None X X XH X XX X X X Tri-state External L H LL L XX X L L–H Q External L H LL L XX X H L–H Tri-state External L H LL H LX L X L–H D External L H LL H LX H L L–H Q External L H LL H LX H H L–H Tri-state Next X X XL H HL H L L–H Q Next X X XL H HL H H L–H Tri-state Next H X XL X HL H L L–H Q Next H X XL X HL H H L–H Tri-state Next X X XL H HL L X L–H D Next H X XL X HL L X L–H D Current X X XL H HH H L L–H Q Current X X XL H HH H H L–H Tri-state Current H X XL X HH H L L–H Q Current H X XL X HH H H L–H Tri-state Current X X XL H HH L X L–H D Current H X XL X HH L X L–H D Notes 5. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 6. WRITE = L when any one or more byte write enable signals and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H. 7. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 8. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only two chip selects CE1 and CE2. 9. The SRAM always initiates ADSP or with the assertion a read cycle when ADSP is asserted, regardless of ADSC. As a result, OE must be driven HIGH of the state of GW, prior to the start of BWE, or the Write BcWycXle. Writes may to allow the occur only outputs to on subsequent tri-state. OE is clocks a don't after care the for the remainder of the write cycle. 10. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-State when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document Number: 38-05540 Rev. *R Page 11 of 38 11 Page

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