CY7C1380DV33 Datasheet PDF - Cypress Semiconductor
Part Number | CY7C1380DV33 | |
Description | 18-Mbit Pipelined SRAM | |
Manufacturers | Cypress Semiconductor | |
Logo | ||
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CY7C1382DV33
18-Mbit (512 K × 36/1 M × 18)
Pipelined SRAM
18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM
Features
■ Supports bus operation up to 200 MHz
■ Available speed grades is 200 MHz
■ Registered inputs and outputs for pipelined operation
■ 3.3 V core power supply
■ 2.5 V or 3.3 V I/O power supply
■ Fast clock-to-output times
❐ 3 ns (for 200 MHz device)
■ Provides high performance 3-1-1-1 access rate
■ User selectable burst counter supporting Intel Pentium®
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed write
■ Asynchronous output enable
■ Single cycle chip deselect
■ CY7C1380DV33 is available in JEDEC-standard Pb-free
100-pin TQFP and 165-ball FBGA package and
CY7C1382DV33 is available in 165-ball FBGA package
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ ZZ sleep mode option
Functional Description
The CY7C1380DV33/CY7C1382DV33 SRAM integrates
524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. All synchronous inputs are gated by
registers controlled by a positive edge triggered clock input
(CLK). The synchronous inputs include all addresses, all data
cinhpiputse,naadbdlerses(sC-pEip2ealinndingCEch3ip[1]e),nabbulrest(CcoEn1t)r,odl einppthu-tesxp(AanDsSioCn,
ADSP, and ADV), write enables (BWX, and BWE), and global
write (GW). Asynchronous inputs include the output enable (OE)
and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP) or address strobe
controller (ADSC) are active. Subsequent burst addresses can
be internally generated as they are controlled by the advance pin
(ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see Pin Definitions on page 6 and Truth Table on
page 10 for further details). Write cycles can be one to two or four
bytes wide as controlled by the byte write control inputs. GW
when active LOW causes all bytes to be written.
The CY7C1380DV33/CY7C1382DV33 operates from a +3.3 V
core power supply while all outputs operate with a +2.5 or +3.3 V
power supply. All inputs and outputs are JEDEC-standard and
JESD8-5-compatible.
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Description
200 MHz
3.0
300
70
167 MHz
3.4
275
70
Unit
ns
mA
mA
Note
1. CE3, CE2 are for 100-pin TQFP and 165-ball FBGA packages only.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-74445 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
February 2, 2012
|
|
CY7C1380DV33
CY7C1382DV33
Pin Configurations (continued)
Figure 2. 165-ball FBGA (13 × 15 × 1.4 mm) pinout (3-Chip Enable)
CY7C1380DV33 (512 K × 36)
123
A NC/288M
B NC/144M
A
A
CE1
CE2
C
DQPC
NC
VDDQ
D
DQC
DQC
VDDQ
E
DQC
DQC
VDDQ
F
DQC
DQC
VDDQ
G
DQC
DQC
VDDQ
H NC NC NC
J
DQD
DQD
VDDQ
K
DQD
DQD
VDDQ
L
DQD
DQD
VDDQ
M
DQD
DQD
VDDQ
N
DQPD
NC
VDDQ
P NC NC/72M A
R MODE NC/36M A
4
BWC
BWD
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
5
BWB
BWA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
TMS
6
CE3
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
A1
A0
7
BWE
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
TCK
8
ADSC
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
9
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
10 11
A NC
A NC/576M
NC/1G
DQB
DQB
DQB
DQB
NC
DQPB
DQB
DQB
DQB
DQB
ZZ
DQA
DQA
DQA
DQA
NC
A
DQA
DQA
DQA
DQA
DQPA
A
AA
123
A NC/288M
B NC/144M
A
A
CE1
CE2
C NC NC VDDQ
D
NC
DQB
VDDQ
E
NC
DQB
VDDQ
F
NC
DQB
VDDQ
G
NC
DQB
VDDQ
H NC NC NC
J DQB NC VDDQ
K DQB NC VDDQ
L DQB NC VDDQ
M DQB NC VDDQ
N DQPB NC VDDQ
P NC NC/72M A
R MODE NC/36M A
CY7C1382DV33 (1 M × 18)
4
BWB
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
5
NC
BWA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
TMS
6
CE3
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
A1
A0
7
BWE
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
TCK
8
ADSC
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
9
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
10 11
AA
A NC/576M
NC/1G
NC
NC
NC
NC
NC
DQPA
DQA
DQA
DQA
DQA
ZZ
DQA
DQA
DQA
DQA
NC
NC
NC
NC
NC
NC
AA
AA
Document Number: 001-74445 Rev. *A
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